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Search results for circuit-output
53
votes
10
answers
1
GATE CSE 2010 | Question: 32
In the sequential circuit shown below, if the initial value of the output $Q_1Q_0$ is $00$. What are the next four values of $Q_1Q_0$? $11$, $10$, $01$, $00$ $10$, $11$, $01$, $00$ $10$, $00$, $01$, $11$ $11$, $10$, $00$, $01$
In the sequential circuit shown below, if the initial value of the output $Q_1Q_0$ is $00$. What are the next four values of $Q_1Q_0$? $11$, $10$, $01$, $00$$10$, $11$, $...
go_editor
30.7k
views
go_editor
asked
Sep 29, 2014
Digital Logic
gatecse-2010
digital-logic
circuit-output
normal
+
–
43
votes
5
answers
2
GATE CSE 1996 | Question: 2.21
Consider the circuit in below figure which has a four bit binary number $b_3b_2b_1b_0$ as input and a five bit binary number, $d_4d_3d_2d_1d_0$ as output. Binary to Hex conversion Binary to BCD conversion Binary to Gray code conversion Binary to $radix-12$ conversion
Consider the circuit in below figure which has a four bit binary number $b_3b_2b_1b_0$ as input and a five bit binary number, $d_4d_3d_2d_1d_0$ as output.Binary to Hex co...
Kathleen
14.1k
views
Kathleen
asked
Oct 9, 2014
Digital Logic
gate1996
digital-logic
circuit-output
normal
+
–
57
votes
4
answers
3
GATE CSE 2002 | Question: 2-1
Consider the following logic circuit whose inputs are functions $f_1, f_2, f_3$ and output is $f$ Given that $f_1(x,y,z) = \Sigma (0,1,3,5)$ $f_2(x,y,z) = \Sigma (6,7),$ and $f(x,y,z) = \Sigma (1,4,5).$ $f_3$ is $\Sigma (1,4,5)$ $\Sigma (6,7)$ $\Sigma (0,1,3,5)$ None of the above
Consider the following logic circuit whose inputs are functions $f_1, f_2, f_3$ and output is $f$Given that$f_1(x,y,z) = \Sigma (0,1,3,5)$$f_2(x,y,z) = \Sigma (6,7),$ and...
Kathleen
14.5k
views
Kathleen
asked
Sep 15, 2014
Digital Logic
gatecse-2002
digital-logic
normal
canonical-normal-form
circuit-output
+
–
62
votes
5
answers
4
GATE CSE 2001 | Question: 2.8
Consider the following circuit with initial state $Q_0 = Q_1 = 0$. The D Flip-flops are positive edged triggered and have set up times 20 nanosecond and hold times $0.$ Consider the following timing diagrams of X and C. The clock period of $C \geq 40$ nanosecond. Which one is the correct plot of Y?
Consider the following circuit with initial state $Q_0 = Q_1 = 0$. The D Flip-flops are positive edged triggered and have set up times 20 nanosecond and hold times $0.$Co...
Kathleen
21.5k
views
Kathleen
asked
Sep 14, 2014
Digital Logic
gatecse-2001
digital-logic
circuit-output
normal
+
–
39
votes
8
answers
5
GATE IT 2007 | Question: 45
The line $T$ in the following figure is permanently connected to the ground. Which of the following inputs $(X_1 X_2 X_3 X_4)$ will detect the fault ? $0000$ $0111$ $1111$ None of these
The line $T$ in the following figure is permanently connected to the ground.Which of the following inputs $(X_1 X_2 X_3 X_4)$ will detect the fault ?$0000$$0111$$1111$Non...
Ishrat Jahan
12.3k
views
Ishrat Jahan
asked
Oct 29, 2014
Digital Logic
gateit-2007
digital-logic
circuit-output
normal
+
–
70
votes
5
answers
6
GATE CSE 2006 | Question: 8
You are given a free running clock with a duty cycle of $50\%$ and a digital waveform $f$ which changes only at the negative edge of the clock. Which one of the following circuits (using clocked D flip-flops) will delay the phase of $f$ by $180°$?
You are given a free running clock with a duty cycle of $50\%$ and a digital waveform $f$ which changes only at the negative edge of the clock. Which one of the following...
Rucha Shelke
18.7k
views
Rucha Shelke
asked
Sep 16, 2014
Digital Logic
gatecse-2006
digital-logic
normal
circuit-output
+
–
66
votes
6
answers
7
GATE CSE 2007 | Question: 36
The control signal functions of a $4$-$bit$ binary counter are given below (where $X$ ... through the following sequence: $0, 3, 4$ $0, 3, 4, 5$ $0, 1, 2, 3, 4$ $0, 1, 2, 3, 4, 5$
The control signal functions of a $4$-$bit$ binary counter are given below (where $X$ is “don’t care”):$$\small {\begin{array}{|c|c|c|c|l|}\hline\textbf{Clear}& ...
Kathleen
19.5k
views
Kathleen
asked
Sep 21, 2014
Digital Logic
gatecse-2007
digital-logic
circuit-output
normal
+
–
44
votes
5
answers
8
GATE CSE 2004 | Question: 61
Consider the partial implementation of a $2-bit$ counter using $T$ flip-flops following the sequence $0-2-3-1-0,$ as shown below. To complete the circuit, the input $X$ should be $Q_2^c$ $Q_2 + Q_1$ $\left(Q_1 + Q_2\right)^c$ $Q_1 \oplus Q_2$
Consider the partial implementation of a $2-bit$ counter using $T$ flip-flops following the sequence $0-2-3-1-0,$ as shown below.To complete the circuit, the input $X$ sh...
Kathleen
19.4k
views
Kathleen
asked
Sep 18, 2014
Digital Logic
gatecse-2004
digital-logic
circuit-output
normal
+
–
24
votes
2
answers
9
GATE CSE 2010 | Question: 9
The Boolean expression of the output $f$ of the multiplexer shown below is $\overline {P \oplus Q \oplus R}$ $P \oplus Q \oplus R$ $P+Q+R$ $\overline{P+Q+R}$
The Boolean expression of the output $f$ of the multiplexer shown below is$\overline {P \oplus Q \oplus R}$$P \oplus Q \oplus R$$P+Q+R$$\overline{P+Q+R}$
go_editor
9.0k
views
go_editor
asked
Sep 29, 2014
Digital Logic
gatecse-2010
digital-logic
circuit-output
easy
+
–
33
votes
9
answers
10
GATE CSE 1993 | Question: 6-3
For the initial state of $000$, the function performed by the arrangement of the $\text{J-K}$ flip-flops in figure is: Shift Register $\text{Mod- 3}$ Counter $\text{Mod- 6}$ Counter $\text{Mod- 2}$ Counter None of the above
For the initial state of $000$, the function performed by the arrangement of the $\text{J-K}$ flip-flops in figure is:Shift Register$\text{Mod- 3}$ Counter$\text{Mod- 6}$...
go_editor
12.7k
views
go_editor
asked
Sep 20, 2015
Digital Logic
gate1993
digital-logic
sequential-circuit
flip-flop
digital-counter
circuit-output
multiple-selects
+
–
37
votes
5
answers
11
GATE IT 2005 | Question: 43
Which of the following input sequences will always generate a $1$ at the output $z$ ...
Which of the following input sequences will always generate a $1$ at the output $z$ at the end of the third cycle?$\begin{array}{|l|l|}\hline \textbf{A} & \textbf{B} & \t...
Ishrat Jahan
15.3k
views
Ishrat Jahan
asked
Nov 3, 2014
Digital Logic
gateit-2005
digital-logic
circuit-output
normal
+
–
0
votes
2
answers
12
UGC NET CSE | December 2018 | Part 2 | Question: 17
Find the boolean expression for the logic circuit shown below: $A \overline{B}$ $\overline{A} B$ $AB$ $\overline{A} \overline{B}$
Find the boolean expression for the logic circuit shown below:$A \overline{B}$$\overline{A} B$$AB$$\overline{A} \overline{B}$
Arjun
3.5k
views
Arjun
asked
Jan 2, 2019
Digital Logic
ugcnetcse-dec2018-paper2
digital-logic
circuit-output
+
–
0
votes
0
answers
13
A sequential circuit has two D flip-flops, two inputs x and y, and one output Z is specified by the following next-state and output equations A(t+1) = xy’ + x B B(t+1) = xA +xB’ Z = A (a) Draw the logic diagram of the circuit. (b) List the state table for the sequential circuit. (c) Draw the corresponding state diagram.
M.Zain
610
views
M.Zain
asked
Dec 30, 2022
Digital Logic
digital-logic
sequential-circuit
output
+
–
0
votes
0
answers
14
A majority function is generated in a combinational circuit when the output is equal to 1 if the input variables have more 1’s than 0’s. The output is 0 otherwise. Make a 3-input majority function.
M.Zain
852
views
M.Zain
asked
Dec 30, 2022
Digital Logic
digital-logic
combinational-circuit
output
+
–
33
votes
7
answers
15
GATE CSE 2006 | Question: 37
Consider the circuit in the diagram. The $\oplus$ operator represents Ex-OR. The D flip-flops are initialized to zeroes (cleared). The following data: $100110000$ is supplied to the “data” terminal in nine clock cycles. After that the values of $q_{2}q_{1}q_{0}$ are: $000$ $001$ $010$ $101$
Consider the circuit in the diagram. The $\oplus$ operator represents Ex-OR. The D flip-flops are initialized to zeroes (cleared).The following data: $100110000$ is suppl...
Rucha Shelke
15.9k
views
Rucha Shelke
asked
Sep 22, 2014
Digital Logic
gatecse-2006
digital-logic
circuit-output
easy
+
–
10
votes
3
answers
16
ISRO2014-21, UGCNET-Dec2012-III: 23, UGCNET-Dec2013-III: 22
What are the final values of $\text{Q}_1$ and $\text{Q}_0$ after $4$ clock cycles, if initial values are $00$ in the sequential circuit shown below: $11$ $01$ $10$ $00$
What are the final values of $\text{Q}_1$ and $\text{Q}_0$ after $4$ clock cycles, if initial values are $00$ in the sequential circuit shown below:$11$$01$$10$$00$
focus _GATE
12.5k
views
focus _GATE
asked
Jul 17, 2015
Digital Logic
isro2014
digital-logic
circuit-output
ugcnetcse-dec2012-paper3
ugcnetcse-dec2013-paper3
+
–
2
votes
2
answers
17
UGC NET CSE | September 2013 | Part 2 | Question: 49
What type of logic circuit is represented by the figure shown below ? $\text{XOR}$ $\text{XNOR}$ $\text{XAND}$ $\text{XNAND}$
What type of logic circuit is represented by the figure shown below ?$\text{XOR}$$\text{XNOR}$$\text{XAND}$$\text{XNAND}$
go_editor
2.0k
views
go_editor
asked
Jul 21, 2016
Digital Logic
ugcnetsep2013ii
digital-logic
circuit-output
+
–
30
votes
4
answers
18
GATE CSE 2010 | Question: 31
What is the boolean expression for the output $f$ of the combinational logic circuit of NOR gates given below? $\overline{Q+R}$ $\overline{P+Q}$ $\overline{P+R}$ $\overline{P+Q+R}$
What is the boolean expression for the output $f$ of the combinational logic circuit of NOR gates given below?$\overline{Q+R}$$\overline{P+Q}$$\overline{P+R}$$\overline{P...
go_editor
11.7k
views
go_editor
asked
Sep 29, 2014
Digital Logic
gatecse-2010
digital-logic
circuit-output
normal
+
–
0
votes
1
answer
19
MadeEasy Workbook: Digital Logic - Circuit Output
How the table is generated?
How the table is generated?
Jyoti Kumari97
481
views
Jyoti Kumari97
asked
Dec 30, 2018
Digital Logic
made-easy-booklet
digital-logic
circuit-output
+
–
3
votes
2
answers
20
MadeEasy CBT 2017:Digital Logic - Circuit Output
Correct result ?
Correct result ?
Vasu_gate2017
1.8k
views
Vasu_gate2017
asked
Jan 22, 2017
Digital Logic
made-easy-test-series
cbt-2017
digital-logic
circuit-output
+
–
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