Search results for combinational / GATE Overflow for GATE CSE

9 votes

3 answers

1

GATE CSE 2023 | Question: 11
The output of a $2$-input multiplexer is connected back to one of its inputs as shown in the figure. Match the functional equivalence of this circuit to one of the following options. $\text{D}$ Flip-flop $\text{D}$ Latch Half-adder Demultiplexer

The output of a $2$-input multiplexer is connected back to one of its inputs as shown in the figure.Match the functional equivalence of this circuit to one of the followi...

admin

10.8k views

admin asked Feb 15, 2023

20 votes

3 answers

2

GATE CSE 2023 | Question: 34
A Boolean digital circuit is composed using two $4$-input multiplexers $\text{(M1 and M2)}$ and one $2$-input multiplexer $\text{(M3)}$ as shown in the figure. $\text{X0-X7}$ are the inputs of the multiplexers $\text{M1 and M2}$ and could be connected to either $0$ or $1.$ The select lines of the ... $(1,1,0,0,1,1,0,1)$ $(1,1,0,1,1,1,0,0)$ $(0,0,1,1,0,1,1,1)$

A Boolean digital circuit is composed using two $4$-input multiplexers $\text{(M1 and M2)}$ and one $2$-input multiplexer $\text{(M3)}$ as shown in the figure. $\text{X0-...

admin

9.5k views

admin asked Feb 15, 2023

17 votes

6 answers

3

GATE CSE 2021 Set 2 | Question: 5
Which one of the following circuits implements the Boolean function given below? $f(x,y,z) = m_0+m_1+m_3+m_4+m_5+m_6$, where $m_i$ is the $i^{\text{th}}$ minterm.

Which one of the following circuits implements the Boolean function given below?$f(x,y,z) = m_0+m_1+m_3+m_4+m_5+m_6$, where $m_i$ is the $i^{\text{th}}$ minterm.

Arjun

9.2k views

Arjun asked Feb 18, 2021

13 votes

2 answers

4

GATE CSE 2022 | Question: 30
Consider a digital display system $\text{(DDS)}$ shown in the figure that displays the contents of register $\text{X}.$ A $16 - \text{bit}$ code word is used to load a word in $\text{X},$ either from $\text{S}$ or from $\text{R}.$ $\text{S}$ is a $1024-$ ... $1:10$ de-multiplexer$; \quad \; \;\text{Q}$ is $1:5$ de-multiplexer$; \quad \text{T}$ is $2:1$ multiplexer

Consider a digital display system $\text{(DDS)}$ shown in the figure that displays the contents of register $\text{X}.$ A $16 – \text{bit}$ code word is used to load a...

Arjun

4.9k views

Arjun asked Feb 15, 2022

5 votes

2 answers

5

GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 53
Consider the following $4$-bit adder circuit. Note, $\text{C}_0$ is carry in and $\text{C}_4$ is carry out for the $4$-bit adder. The given circuit operates on $\text{2's}$ ... $\text{S}=1$

Consider the following $4$-bit adder circuit.Note, $\text{C}_0$ is carry in and $\text{C}_4$ is carry out for the $4$-bit adder. The given circuit operates on $\text{2's}...

GO Classes

696 views

GO Classes asked Jan 21

4 votes

1 answer

6

GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 21
How many $\text{4-to-1}$ multiplexers are needed to implement a $\text{64-to-1}$ multiplexer?

How many $\text{4-to-1}$ multiplexers are needed to implement a $\text{64-to-1}$ multiplexer?

GO Classes

410 views

GO Classes asked Jan 21

4 votes

2 answers

7

GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 60
You are asked to implement the following four functions with half-adders: ... of half-adders required to implement all four functions simultaneously? (You are not allowed to use any other logic element but half-adder)

You are asked to implement the following four functions with half-adders:$$\begin{aligned}& \mathrm{f}_1=A \oplus B \oplus C \\& \mathrm{f}_2=A^{\prime} B C+A B^{\prime} ...

GO Classes

494 views

GO Classes asked Jan 28

2 votes

1 answer

8

GO Classes Test Series 2024 | Mock GATE | Test 14 | Question: 28
Consider function $\mathbf{G}(\mathbf{A}, \mathbf{B}, \mathbf{C})=\mathbf{A B}+\mathbf{B C}$. Let $\mathbf{F}(\mathbf{A}, \mathbf{B}, \mathbf{C})$ ... input to a 2-to-1 multiplexer. The correct implementation of $\mathbf{F}(\mathbf{A}, \mathbf{B}, \mathbf{C})$ is shown in:

Consider function $\mathbf{G}(\mathbf{A}, \mathbf{B}, \mathbf{C})=\mathbf{A B}+\mathbf{B C}$. Let $\mathbf{F}(\mathbf{A}, \mathbf{B}, \mathbf{C})$ be the dual of $\mathbf...

GO Classes

524 views

GO Classes asked Feb 5

4 votes

1 answer

9

GO Classes Test Series 2024 | Mock GATE | Test 11 | Question: 40
What is the output, $f(a,b,c,d),$ for the following circuit? $\Sigma(1,3,6,13,14,15)$ $\Sigma(1,3,6,9,10,14)$ $\Sigma(1,3,5,6,9,10,14)$ $\Sigma(1,3,5,6,9,10,12)$

What is the output, $f(a,b,c,d),$ for the following circuit?$\Sigma(1,3,6,13,14,15)$$\Sigma(1,3,6,9,10,14)$$\Sigma(1,3,5,6,9,10,14)$$\Sigma(1,3,5,6,9,10,12)$

GO Classes

550 views

GO Classes asked Jan 13

3 votes

0 answers

10

GO Classes Test Series 2024 | Mock GATE | Test 14 | Question: 60
The logic circuit above is used to compare two unsigned 2-bit numbers, $X_1 X_0=X$ and $Y_1 Y_0=Y$, where $X_0$ and $Y_0$ are the least significant bits. (A small circle on any line in a logic diagram indicates logical NOT.) Which of the following always makes the output $Z$ have the value 1? $X\gt Y$ $X\lt Y$ $X=Y$ $X \neq Y$

The logic circuit above is used to compare two unsigned 2-bit numbers, $X_1 X_0=X$ and $Y_1 Y_0=Y$, where $X_0$ and $Y_0$ are the least significant bits. (A small circle ...

GO Classes

341 views

GO Classes asked Feb 5

3 votes

1 answer

11

GO Classes Test Series 2024 | Mock GATE | Test 11 | Question: 16
Which one of the following options is CORRECT for the given logic circuit? $P=1, Q=1 ; X=0$ $P=1, Q=0 ; X=1$ $P=0, Q=1 ; X=0$ $P=0, Q=0 ; X=1$

Which one of the following options is CORRECT for the given logic circuit?$P=1, Q=1 ; X=0$$P=1, Q=0 ; X=1$$P=0, Q=1 ; X=0$$P=0, Q=0 ; X=1$

GO Classes

398 views

GO Classes asked Jan 13

2 votes

1 answer

12

GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 22
What is the output for the following circuit? $w=\overline{b} c$ $w=b \oplus c$ $w=\overline{b \oplus c}$ $w=\overline{b}+\overline{c}$

What is the output for the following circuit?$w=\overline{b} c$$w=b \oplus c$$w=\overline{b \oplus c}$$w=\overline{b}+\overline{c}$

GO Classes

398 views

GO Classes asked Jan 21

0 votes

2 answers

13

Digital Logic | Sample question
The number of full and half-adders required to add $32$-bit numbers is______________________

The number of full and half-adders required to add $32$-bit numbers is______________________

rajveer43

204 views

rajveer43 asked Jan 12

0 votes

1 answer

14

ISRO 2024
A full adder circuit requires two inputs and two outputs two inputs and three outputs three inputs and two outputs three inputs and one output A request to the approver.!! This question is asked in ISRO 2024. Due to insufficient points, couldn’t add ‘isro2024’ tag, Please add it.

A full adder circuit requirestwo inputs and two outputstwo inputs and three outputsthree inputs and two outputsthree inputs and one outputA request to the approver.!!This...

Ramayya

141 views

Ramayya asked Jan 7

1 votes

1 answer

15

Doubt in NAND and NOR gate.
Why NAND gate is preferred over NOR gate?

Why NAND gate is preferred over NOR gate?

prajjwal_191

151 views

prajjwal_191 asked Dec 9, 2023

0 votes

1 answer

16

Digital Logic Made Easy OTS

Sajal Mallick

272 views

Sajal Mallick asked Nov 18, 2023

0 votes

0 answers

17

Madeeasy ots Digital Logic Combinational Circuits
I am confused in active low enable input and active low output?

I am confused in active low enable input and active low output?

Sajal Mallick

214 views

Sajal Mallick asked Nov 23, 2023

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