Login
Register
Dark Mode
Brightness
Profile
Edit Profile
Messages
My favorites
My Updates
Logout
Search results for digital
27
votes
5
answers
21
GATE CSE 2004 | Question: 66
Let $A = 1111 1010$ and $B = 0000 1010$ be two $8-bit$ $2’s$ complement numbers. Their product in $2’s$ complement is $1100 0100$ $1001 1100$ $1010 0101$ $1101 0101$
Let $A = 1111 1010$ and $B = 0000 1010$ be two $8-bit$ $2’s$ complement numbers. Their product in $2’s$ complement is$1100 0100$$1001 1100$$1010 0101$$1101 0101$
Kathleen
19.2k
views
Kathleen
asked
Sep 18, 2014
Digital Logic
gatecse-2004
digital-logic
number-representation
easy
+
–
33
votes
2
answers
22
GATE CSE 1996 | Question: 1.21
A ROM is used to store the table for multiplication of two $8$-bit unsigned integers. The size of ROM required is $256 \times 16$ $64 K \times 8$ $4 K \times 16$ $64 K \times 16$
A ROM is used to store the table for multiplication of two $8$-bit unsigned integers. The size of ROM required is$256 \times 16$$64 K \times 8$$4 K \times 16$$64 K \times...
Kathleen
18.7k
views
Kathleen
asked
Oct 9, 2014
Digital Logic
gate1996
digital-logic
normal
rom
+
–
52
votes
6
answers
23
GATE CSE 2014 Set 2 | Question: 7
Let $k=2^n$. A circuit is built by giving the output of an $n$-bit binary counter as input to an $n\text{-to-}2^n$ bit decoder. This circuit is equivalent to a $k$-bit binary up counter. $k$-bit binary down counter. $k$--bit ring counter. $k$-bit Johnson counter.
Let $k=2^n$. A circuit is built by giving the output of an $n$-bit binary counter as input to an $n\text{-to-}2^n$ bit decoder. This circuit is equivalent to a $k$-bit bi...
go_editor
19.8k
views
go_editor
asked
Sep 28, 2014
Digital Logic
gatecse-2014-set2
digital-logic
normal
digital-counter
+
–
9
votes
3
answers
24
GATE CSE 2023 | Question: 11
The output of a $2$-input multiplexer is connected back to one of its inputs as shown in the figure. Match the functional equivalence of this circuit to one of the following options. $\text{D}$ Flip-flop $\text{D}$ Latch Half-adder Demultiplexer
The output of a $2$-input multiplexer is connected back to one of its inputs as shown in the figure.Match the functional equivalence of this circuit to one of the followi...
admin
10.8k
views
admin
asked
Feb 15, 2023
Digital Logic
gatecse-2023
digital-logic
combinational-circuit
multiplexer
1-mark
+
–
53
votes
5
answers
25
GATE CSE 1991 | Question: 5-c
Find the maximum clock frequency at which the counter in the figure below can be operated. Assume that the propagation delay through each flip flop and each AND gate is $10\;\text{ns}$. Also, assume that the setup time for the $JK$ inputs of the flip flops is negligible.
Find the maximum clock frequency at which the counter in the figure below can be operated. Assume that the propagation delay through each flip flop and each AND gate is $...
ibia
23.2k
views
ibia
asked
Nov 14, 2015
Digital Logic
gate1991
digital-logic
sequential-circuit
flip-flop
digital-counter
+
–
3
votes
3
answers
26
UGC NET CSE | December 2013 | Part 2 | Question: 32
Given that $(292)_{10} = (1204)_x$ in some number system $x$. The base $x$ of that number system is 2 8 10 None of the above
Given that $(292)_{10} = (1204)_x$ in some number system $x$. The base $x$ of that number system is2810None of the above
go_editor
30.1k
views
go_editor
asked
Jul 26, 2016
Digital Logic
ugcnetcse-dec2013-paper2
digital-logic
number-system
+
–
53
votes
3
answers
27
GATE CSE 2010 | Question: 8
$P$ is a $16$-bit signed integer. The $2$'s complement representation of $P$ is $(F87B)_{16}$. The $2$'s complement representation of $8\times P$ is $(C3D8)_{16}$ $(187B)_{16}$ $(F878)_{16}$ $(987B)_{16}$
$P$ is a $16$-bit signed integer. The $2$'s complement representation of $P$ is $(F87B)_{16}$. The $2$'s complement representation of $8\times P$ is$(C3D8)_{16}$$(187B)_{...
go_editor
16.4k
views
go_editor
asked
Sep 29, 2014
Digital Logic
gatecse-2010
digital-logic
number-representation
normal
+
–
20
votes
3
answers
28
GATE CSE 2023 | Question: 34
A Boolean digital circuit is composed using two $4$-input multiplexers $\text{(M1 and M2)}$ and one $2$-input multiplexer $\text{(M3)}$ as shown in the figure. $\text{X0-X7}$ are the inputs of the multiplexers $\text{M1 and M2}$ and could be connected to either $0$ or $1.$ The select lines of the ... $(1,1,0,0,1,1,0,1)$ $(1,1,0,1,1,1,0,0)$ $(0,0,1,1,0,1,1,1)$
A Boolean digital circuit is composed using two $4$-input multiplexers $\text{(M1 and M2)}$ and one $2$-input multiplexer $\text{(M3)}$ as shown in the figure. $\text{X0-...
admin
9.5k
views
admin
asked
Feb 15, 2023
Digital Logic
gatecse-2023
digital-logic
combinational-circuit
multiplexer
2-marks
+
–
54
votes
5
answers
29
GATE CSE 2007 | Question: 48
Which of the following is TRUE about formulae in Conjunctive Normal Form? For any formula, there is a truth assignment for which at least half the clauses evaluate to true. For any formula, there is a truth assignment for which all the clauses ... formula such that for each truth assignment, at most one-fourth of the clauses evaluate to true. None of the above.
Which of the following is TRUE about formulae in Conjunctive Normal Form?For any formula, there is a truth assignment for which at least half the clauses evaluate to true...
Kathleen
15.0k
views
Kathleen
asked
Sep 21, 2014
Digital Logic
gatecse-2007
digital-logic
normal
conjunctive-normal-form
+
–
56
votes
12
answers
30
GATE CSE 2015 Set 2 | Question: 37
The number of min-terms after minimizing the following Boolean expression is _______. $[D'+AB'+A'C+AC'D+A'C'D]'$
The number of min-terms after minimizing the following Boolean expression is _______.$[D'+AB'+A'C+AC'D+A'C'D]'$
go_editor
19.4k
views
go_editor
asked
Feb 12, 2015
Digital Logic
gatecse-2015-set2
digital-logic
boolean-algebra
normal
numerical-answers
+
–
21
votes
6
answers
31
GATE CSE 2021 Set 1 | Question: 42
Consider the following Boolean expression. $F=(X+Y+Z)(\overline X +Y)(\overline Y +Z)$ Which of the following Boolean expressions is/are equivalent to $\overline F$ (complement of $F$ ... $X\overline Y +Y\overline Z + \overline X\; \overline Y \;\overline Z$
Consider the following Boolean expression.$F=(X+Y+Z)(\overline X +Y)(\overline Y +Z)$Which of the following Boolean expressions is/are equivalent to $\overline F$ (comple...
Arjun
10.3k
views
Arjun
asked
Feb 18, 2021
Digital Logic
gatecse-2021-set1
multiple-selects
digital-logic
boolean-algebra
2-marks
+
–
17
votes
6
answers
32
GATE CSE 2021 Set 2 | Question: 5
Which one of the following circuits implements the Boolean function given below? $f(x,y,z) = m_0+m_1+m_3+m_4+m_5+m_6$, where $m_i$ is the $i^{\text{th}}$ minterm.
Which one of the following circuits implements the Boolean function given below?$f(x,y,z) = m_0+m_1+m_3+m_4+m_5+m_6$, where $m_i$ is the $i^{\text{th}}$ minterm.
Arjun
9.2k
views
Arjun
asked
Feb 18, 2021
Digital Logic
gatecse-2021-set2
digital-logic
combinational-circuit
multiplexer
1-mark
+
–
41
votes
6
answers
33
GATE CSE 1999 | Question: 2.16
The number of full and half-adders required to add $16$-bit numbers is $8$ half-adders, $8$ full-adders $1$ half-adder, $15$ full-adders $16$ half-adders, $0$ full-adders $4$ half-adders, $12$ full-adders
The number of full and half-adders required to add $16$-bit numbers is$8$ half-adders, $8$ full-adders$1$ half-adder, $15$ full-adders$16$ half-adders, $0$ full-adders$4$...
Kathleen
22.5k
views
Kathleen
asked
Sep 23, 2014
Digital Logic
gate1999
digital-logic
normal
adder
+
–
46
votes
8
answers
34
GATE CSE 2015 Set 1 | Question: 37
A positive edge-triggered $D$ flip-flop is connected to a positive edge-triggered $JK$ flip-flop as follows. The $Q$ output of the $D$ flip-flop is connected to both the $J$ and $K$ inputs of the $JK$ ... $JK$ flip-flops. Both the flip-flops have non-zero propagation delays. $0110110\ldots$ $0100100\ldots$ $011101110\ldots$ $011001100\ldots$
A positive edge-triggered $D$ flip-flop is connected to a positive edge-triggered $JK$ flip-flop as follows. The $Q$ output of the $D$ flip-flop is connected to both the ...
makhdoom ghaya
13.1k
views
makhdoom ghaya
asked
Feb 13, 2015
Digital Logic
gatecse-2015-set1
digital-logic
flip-flop
normal
+
–
37
votes
5
answers
35
GATE CSE 1999 | Question: 2.9
Which of the following sets of component(s) is/are sufficient to implement any arbitrary Boolean function? XOR gates, NOT gates $2$ to $1$ multiplexers AND gates, XOR gates Three-input gates that output $(A.B) + C$ for the inputs $A, B$ and $C$.
Which of the following sets of component(s) is/are sufficient to implement any arbitrary Boolean function?XOR gates, NOT gates$2$ to $1$ multiplexersAND gates, XOR gatesT...
Kathleen
15.2k
views
Kathleen
asked
Sep 23, 2014
Digital Logic
gate1999
digital-logic
normal
functional-completeness
multiple-selects
+
–
29
votes
6
answers
36
GATE CSE 2021 Set 2 | Question: 44
If the numerical value of a $2$-byte unsigned integer on a little endian computer is $255$ more than that on a big endian computer, which of the following choices represent(s) the unsigned integer on a little endian computer? $0\text{x}6665$ $0\text{x} 0001$ $0\text{x} 4243$ $0\text{x} 0100$
If the numerical value of a $2$-byte unsigned integer on a little endian computer is $255$ more than that on a big endian computer, which of the following choices represe...
Arjun
14.5k
views
Arjun
asked
Feb 18, 2021
Digital Logic
gatecse-2021-set2
multiple-selects
digital-logic
number-representation
little-endian-big-endian
2-marks
+
–
34
votes
9
answers
37
GATE CSE 2016 Set 1 | Question: 07
The $16\text{-bit}\;2's$ complement representation of an integer is $1111 \quad 1111 \quad 1111 \quad 0101;$ its decimal representation is ____________
The $16\text{-bit}\;2's$ complement representation of an integer is $1111 \quad 1111 \quad 1111 \quad 0101;$ its decimal representation is ____________
Sandeep Singh
12.3k
views
Sandeep Singh
asked
Feb 12, 2016
Digital Logic
gatecse-2016-set1
digital-logic
number-representation
normal
numerical-answers
+
–
5
votes
2
answers
38
Morris Mano Edition 3 Exercise 2 Question 12 (Page No. 70)
Express the following function in the sum of minterms and The product of the maxterms. (a) F(A,B,C,D) = B’D + A’D + BD (b)F(x,y,z)=(xy + z)(xz + y)
Express the following function in the sum of minterms and The product of the maxterms.(a) F(A,B,C,D) = B’D + A’D + BD(b)F(x,y,z)=(xy + z)(xz + y)
ajaysoni1924
35.4k
views
ajaysoni1924
asked
Mar 31, 2019
Digital Logic
digital-logic
morris-mano
boolean-algebra
simplification
+
–
43
votes
5
answers
39
GATE CSE 1996 | Question: 2.21
Consider the circuit in below figure which has a four bit binary number $b_3b_2b_1b_0$ as input and a five bit binary number, $d_4d_3d_2d_1d_0$ as output. Binary to Hex conversion Binary to BCD conversion Binary to Gray code conversion Binary to $radix-12$ conversion
Consider the circuit in below figure which has a four bit binary number $b_3b_2b_1b_0$ as input and a five bit binary number, $d_4d_3d_2d_1d_0$ as output.Binary to Hex co...
Kathleen
14.1k
views
Kathleen
asked
Oct 9, 2014
Digital Logic
gate1996
digital-logic
circuit-output
normal
+
–
45
votes
4
answers
40
GATE CSE 2017 Set 2 | Question: 12
Given the following binary number in $32$-bit (single precision) $\text{IEEE-754}$ format : $\large 00111110011011010000000000000000$ The decimal value closest to this floating-point number is : $1.45*10^1$ $1.45*10^{-1}$ $2.27*10^{-1}$ $2.27*10^1$
Given the following binary number in $32$-bit (single precision) $\text{IEEE-754}$ format : $\large 00111110011011010000000000000000$Th...
khushtak
21.9k
views
khushtak
asked
Feb 14, 2017
Digital Logic
gatecse-2017-set2
digital-logic
number-representation
floating-point-representation
ieee-representation
+
–
Page:
« prev
1
2
3
4
next »
Email or Username
Show
Hide
Password
I forgot my password
Remember
Log in
Register