Search results for flip-flop / GATE Overflow for GATE CSE

113 votes

20 answers

1

GATE CSE 2016 Set 1 | Question: 8
We want to design a synchronous counter that counts the sequence $0-1-0-2-0-3$ and then repeats. The minimum number of $\text{J-K}$ flip-flops required to implement this counter is _____________.

We want to design a synchronous counter that counts the sequence $0-1-0-2-0-3$ and then repeats. The minimum number of $\text{J-K}$ flip-flops required to implement this ...

Sandeep Singh

52.2k views

Sandeep Singh asked Feb 12, 2016

41 votes

9 answers

2

GATE CSE 2018 | Question: 22
Consider the sequential circuit shown in the figure, where both flip-flops used are positive edge-triggered $\text{D}$ flip-flops. The number of states in the state transition diagram of this circuit that have a transition back to the same state on some value of "in" is ____

Consider the sequential circuit shown in the figure, where both flip-flops used are positive edge-triggered $\text{D}$ flip-flops.The number of states in the state trans...

gatecse

23.2k views

gatecse asked Feb 14, 2018

47 votes

9 answers

3

GATE CSE 2004 | Question: 18, ISRO2007-31
In an $SR$ latch made by cross-coupling two NAND gates, if both $S$ and $R$ inputs are set to $0$, then it will result in $Q = 0, Q' = 1$ $Q = 1, Q' = 0$ $Q = 1, Q' = 1$ Indeterminate states

In an $SR$ latch made by cross-coupling two NAND gates, if both $S$ and $R$ inputs are set to $0$, then it will result in$Q = 0, Q' = 1$$Q = 1, Q' = 0$$Q = 1, Q' = 1$Inde...

Kathleen

22.3k views

Kathleen asked Sep 18, 2014

53 votes

5 answers

4

GATE CSE 1991 | Question: 5-c
Find the maximum clock frequency at which the counter in the figure below can be operated. Assume that the propagation delay through each flip flop and each AND gate is $10\;\text{ns}$. Also, assume that the setup time for the $JK$ inputs of the flip flops is negligible.

Find the maximum clock frequency at which the counter in the figure below can be operated. Assume that the propagation delay through each flip flop and each AND gate is $...

ibia

23.2k views

ibia asked Nov 14, 2015

46 votes

8 answers

5

GATE CSE 2015 Set 1 | Question: 37
A positive edge-triggered $D$ flip-flop is connected to a positive edge-triggered $JK$ flip-flop as follows. The $Q$ output of the $D$ flip-flop is connected to both the $J$ and $K$ inputs of the $JK$ ... $JK$ flip-flops. Both the flip-flops have non-zero propagation delays. $0110110\ldots$ $0100100\ldots$ $011101110\ldots$ $011001100\ldots$

A positive edge-triggered $D$ flip-flop is connected to a positive edge-triggered $JK$ flip-flop as follows. The $Q$ output of the $D$ flip-flop is connected to both the ...

makhdoom ghaya

13.1k views

makhdoom ghaya asked Feb 13, 2015

6 votes

1 answer

6

GATE CSE 2023 | Question: 33
Consider a sequential digital circuit consisting of $\mathrm{T}$ flip-flops and $\mathrm{D}$ flip-flops as shown in the figure. $\text{CLKIN}$ is the clock input to the circuit. At the beginning, $\text{Q1, Q2}$ and $\text{Q3}$ have values $0,1$ and $1,$ respectively. ... $\text{NEVER}$ be obtained with this digital circuit? $(0,0,1)$ $(1,0,0)$ $(1,0,1)$ $(1,1,1)$

Consider a sequential digital circuit consisting of $\mathrm{T}$ flip-flops and $\mathrm{D}$ flip-flops as shown in the figure. $\text{CLKIN}$ is the clock input to the c...

admin

9.1k views

admin asked Feb 15, 2023

2 votes

2 answers

7

GO Classes Test Series 2024 | Mock GATE | Test 11 | Question: 39
The circuit shown below is designed using two multiplexers. This circuit is equivalent to: a positive edge triggered $\mathrm{T}$ flip flop a negative edge triggered $\mathrm{T}$ flip flop a negative edge triggered $\text{D}$ flip flop a positive edge triggered $\mathrm{D}$ flip flop

The circuit shown below is designed using two multiplexers.This circuit is equivalent to:a positive edge triggered $\mathrm{T}$ flip flopa negative edge triggered $\mathr...

GO Classes

838 views

GO Classes asked Jan 13

3 votes

1 answer

8

GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 52
Consider the sequential circuit shown below. Consider the following state assignment: $\text{A}$ stands for $\text{Q = 0, B}$ stands for $\text{Q = 1}.$ The state transition diagram for the circuit above is shown in: a b c d

Consider the sequential circuit shown below.Consider the following state assignment: $\text{A}$ stands for $\text{Q = 0, B}$ stands for $\text{Q = 1}.$ The state transiti...

GO Classes

654 views

GO Classes asked Jan 21

2 votes

1 answer

9

GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 51
We would like to use a $\text{T}$ flip-flop and design a circuit that works like a $\text{J-K}$ flip-flop. The simplified input to the $\text{T}$ flip-flop should be: $\mathrm{T}=\mathrm{J}=\mathrm{K}$ $\text{T}=\text{JQ}^{\prime}+\text{K}^{\prime} Q$ $\text{T}=\text{JQ}^{\prime}+K Q$ $\text{T}=\text{JQ}+\text{KQ}'$

We would like to use a $\text{T}$ flip-flop and design a circuit that works like a $\text{J-K}$ flip-flop. The simplified input to the $\text{T}$ flip-flop should be:$\ma...

GO Classes

483 views

GO Classes asked Jan 21

0 votes

0 answers

10

GFG CSE Mock 2018 | Sequential Circuits
Consider following counters: Counter-1: Counter-2: Which of the following option is correct? Counter-1 is a three-bit "counter" which counts $0, 1, 2, 4, 5, 7, 0, ... . $ ... $0, 1, 2, 3, 5, 6, 0, ... $.

Consider following counters:Counter-1: Counter-2: Which of the following option is correct? Counter-1 is a three-bit "counter" which counts $0, 1, 2, 4, 5, 7, 0, ... . $ ...

rajveer43

112 views

rajveer43 asked Jan 12

21 votes

5 answers

11

GATE CSE 1990 | Question: 5-c
For the synchronous counter shown in Fig$.3,$ write the truth table of $Q_{0}, Q_{1}$, and $Q_{2}$ after each pulse, starting from $Q_{0}=Q_{1}=Q_{2}=0$ and determine the counting sequence and also the modulus of the counter.

For the synchronous counter shown in Fig$.3,$ write the truth table of $Q_{0}, Q_{1}$, and $Q_{2}$ after each pulse, starting from $Q_{0}=Q_{1}=Q_{2}=0$ and determine the...

makhdoom ghaya

6.4k views

makhdoom ghaya asked Nov 23, 2016

3 votes

0 answers

12

[Self Doubt] Conversion of SR-flipflop to T-flipflop
The standard approach for solving such problem is as follows: This approach gives us the equation for $S$ & $R$ in terms of $T, Q$ as $S = T\overline Q \qquad \to (1)$ $R = TQ \qquad \to (2)$ I tried using a different ... & $(7)$, we get $S=T\overline{Q}$ and $R=TQ$ which is consistent with the standard approach and maintains $SR=0$

The standard approach for solving such problem is as follows:This approach gives us the equation for $S$ & $R$ in terms of $T, Q$ as$S = T\overline Q \qquad \to (1)$$R = ...

thehitchh1ker

303 views

thehitchh1ker asked Oct 31, 2023

33 votes

9 answers

13

GATE CSE 1993 | Question: 6-3
For the initial state of $000$, the function performed by the arrangement of the $\text{J-K}$ flip-flops in figure is: Shift Register $\text{Mod- 3}$ Counter $\text{Mod- 6}$ Counter $\text{Mod- 2}$ Counter None of the above

For the initial state of $000$, the function performed by the arrangement of the $\text{J-K}$ flip-flops in figure is:Shift Register$\text{Mod- 3}$ Counter$\text{Mod- 6}$...

go_editor

12.7k views

go_editor asked Sep 20, 2015

47 votes

5 answers

14

GATE IT 2007 | Question: 7
Which of the following input sequences for a cross-coupled $R-S$ flip-flop realized with two $NAND$ gates may lead to an oscillation? $11, 00$ $01, 10$ $10, 01$ $00, 11$

Which of the following input sequences for a cross-coupled $R-S$ flip-flop realized with two $NAND$ gates may lead to an oscillation?$11, 00$$01, 10$$10, 01$$00, 11$

Ishrat Jahan

22.5k views

Ishrat Jahan asked Oct 29, 2014

8 votes

3 answers

15

ISRO-2013-30
In a three stage counter, using $RS$ flip flops what will be the value of the counter after giving $9$ pulses to its input ? Assume that the value of counter before giving any pulses is $1$ : $1$ $2$ $9$ $10$

In a three stage counter, using $RS$ flip flops what will be the value of the counter after giving $9$ pulses to its input ? Assume that the value of counter before givin...

makhdoom ghaya

6.0k views

makhdoom ghaya asked Apr 27, 2016

29 votes

7 answers

16

GATE CSE 2017 Set 1 | Question: 33
Consider a combination of $\text{T}$ and $\text{D}$ flip-flops connected as shown below. The output of the $\text{D}$ flip-flop is connected to the input of the $\text{T}$ flip-flop and the output of the $\text{T}$ flip-flop is connected to the input of ... $3^{\text{rd}}$ cycle are $01$ and after the $4^{\text{th}}$ cycle are $01$ respectively.

Consider a combination of $\text{T}$ and $\text{D}$ flip-flops connected as shown below. The output of the $\text{D}$ flip-flop is connected to the input of the $\text{T}...

Arjun

14.8k views

Arjun asked Feb 14, 2017

0 votes

1 answer

17

Made easy workbook

rishabh-441

263 views

rishabh-441 asked Jun 1, 2023

1 votes

1 answer

18

GO Classes 2023 | IIITH Mock Test 1 | Question: 37
A new flip-flop, called AB flip-flop, is created as shown below. What does the flip-flop do? Set command when $A = 0 , B = 0$ Reset command when $A = 0 , B = 1$ Hold command when $A = 1 ,B = 0$ Toggle command when $A = 1 , B = 1$

A new flip-flop, called AB flip-flop, is created as shown below. What does the flip-flop do?Set command when $A = 0 , B = 0$Reset command when $A = 0 , B = 1$Hold command...

GO Classes

615 views

GO Classes asked Mar 26, 2023

1 votes

1 answer

19

GO Classes 2023 | IIITH Mock Test 1 | Question: 38
In an $SR$ latch created by cross-coupling two NOR gates, which of the following values for $S$ and $R$ will lead to an indeterminate state? $S = 0, R = 0$ $S = 0, R = 1$ $S = 1, R = 0$ $S = 1, R = 1$

In an $SR$ latch created by cross-coupling two NOR gates, which of the following values for $S$ and $R$ will lead to an indeterminate state?$S = 0, R = 0$$S = 0, R = 1$$S...

GO Classes

610 views

GO Classes asked Mar 26, 2023

2 votes

1 answer

20

GATE CSE 2023 | Memory Based Question: 22
The initial state of a given sequential circuit is $Q_0 Q_1 Q_2=011$. Which of the following state does not occur $101$ $111$ $001$ $100$

The initial state of a given sequential circuit is $Q_0 Q_1 Q_2=011$. Which of the following state does not occur$101$$111$$001$$100$

GO Classes

1.1k views

GO Classes asked Feb 5, 2023

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