Search results for interrupts / GATE Overflow for GATE CSE

55 votes

5 answers

1

GATE CSE 2007 | Question: 71
Consider the following program segment. Here $\text{R1, R2}$ and $\text{R3}$ ... word addressable. The number of memory references for accessing the data in executing the program completely is $10$ $11$ $20$ $21$

Consider the following program segment. Here $\text{R1, R2}$ and $\text{R3}$ are the general purpose registers.$$\begin{array}{|l|l|l|c|} \hline & \text {Instruction} & \...

Kathleen

22.2k views

Kathleen asked Sep 21, 2014

11 votes

2 answers

2

GATE CSE 2023 | Question: 24
A keyboard connected to a computer is used at a rate of $1$ keystroke per second. The computer system polls the keyboard every $10 \mathrm{~ms}$ (milli seconds) to check for a keystroke and consumes $100\; \mu \mathrm{s}$ (micro seconds) for ... interrupt and processing a keystroke. The ratio $\dfrac{T_{1}}{T_{2}}$ is _____________. (Rounded off to one decimal place)

A keyboard connected to a computer is used at a rate of $1$ keystroke per second. The computer system polls the keyboard every $10 \mathrm{~ms}$ (milli seconds) to check ...

admin

8.0k views

admin asked Feb 15, 2023

51 votes

5 answers

3

GATE CSE 2005 | Question: 69
A device with data transfer rate $10$ KB/sec is connected to a CPU. Data is transferred byte-wise. Let the interrupt overhead be $4\mu$sec. The byte transfer time between the device interface register and CPU or memory is negligible. What is ... gain of operating the device under interrupt mode over operating it under program-controlled mode? $15$ $25$ $35$ $45$

A device with data transfer rate $10$ KB/sec is connected to a CPU. Data is transferred byte-wise. Let the interrupt overhead be $4\mu$sec. The byte transfer time between...

Kathleen

19.5k views

Kathleen asked Sep 22, 2014

0 votes

1 answer

4

ISRO 2024
Which of the following is false about interrupts? Interrupts can be triggered by a hardware or a software Hardware interrupts may be triggered by sending a signal to CPU through a system bus Software interrupts may be triggered by executing system calls Trap is a hardware generated interrupt

Which of the following is false about interrupts?Interrupts can be triggered by a hardware or a softwareHardware interrupts may be triggered by sending a signal to CPU th...

Ramayya

264 views

Ramayya asked Jan 7

0 votes

0 answers

5

ISRO 2024
In a vectored interrupt The branch address is assigned to a fixed location in a memory The interrupting source supplies the branch information to the processor The branch address is obtained from a register in the processor None of the above A request to the approver.!! This question is asked in ISRO 2024. Due to insufficient points, couldn’t add ‘isro2024’ tag, Please add it.

In a vectored interruptThe branch address is assigned to a fixed location in a memoryThe interrupting source supplies the branch information to the processorThe branch ad...

Ramayya

128 views

Ramayya asked Jan 7

1 votes

1 answer

6

COA - DMA
A hard disk with a transfer rate of 1 Mbytes/ second is constantly transferring data to memory using DMA. The processor runs at 500 MHz, and takes 500 and 1000 clock cycles to initiate and complete DMA transfer respectively. If the size of the transfer is 1 Kbytes, what is the percentage of processor time consumed for the transfer operation?________(Rounded off to three decimal)

A hard disk with a transfer rate of 1 Mbytes/ second is constantly transferring data to memory using DMA. The processor runs at 500 MHz, and takes 500 and 1000 clock cycl...

ajayraho

610 views

ajayraho asked Nov 21, 2023

3 votes

2 answers

7

I/O Modes | Process State Transition | COA & OS
MSQ A ‘Running’ process is surely put into ‘Blocked/Wait’ state during while requesting for an I/O, in which of the following I/O modes? Synchronous I/O Asynchronous I/O Interrupt Driven I/O DMA

MSQA ‘Running’ process is surely put into ‘Blocked/Wait’ state during while requesting for an I/O, in which of the following I/O modes?Synchronous I/OAsynchronous...

Souvik33

797 views

Souvik33 asked Dec 2, 2022

0 votes

0 answers

8

COA
Which of the following is/are true for a CPU which does not have any stack pointer registers? A Interrupts are not possible. B All subroutine calls and interrupts are possible. C It cannot have nested subroutines call. D It cannot have subroutine call instruction.

Which of the following is/are true for a CPU which does not have any stack pointer registers?A Interrupts are not possible. B All subroutine calls and interrupts are po...

Overflow04

510 views

Overflow04 asked Jan 24, 2023

26 votes

4 answers

9

GATE CSE 2009 | Question: 8, UGCNET-June2012-III: 58
A CPU generally handles an interrupt by executing an interrupt service routine: As soon as an interrupt is raised. By checking the interrupt register at the end of fetch cycle. By checking the interrupt register after finishing the execution of the current instruction. By checking the interrupt register at fixed time intervals.

A CPU generally handles an interrupt by executing an interrupt service routine:As soon as an interrupt is raised.By checking the interrupt register at the end of fetch cy...

Kathleen

16.0k views

Kathleen asked Sep 22, 2014

2 votes

1 answer

10

Andrew S. Tanenbaum (OS) Edition 4 Exercise 5 Question 8 (Page No. 430)
Suppose that a computer can read or write a memory word in $5 nsec.$ Also suppose that when an interrupt occurs, all $32$ CPU registers, plus the program counter and PSW are pushed onto the stack. What is the maximum number of interrupts per second this machine can process?

Suppose that a computer can read or write a memory word in $5 nsec.$ Also suppose that when an interrupt occurs, all $32$ CPU registers, plus the program counter and PSW ...

admin

430 views

admin asked Oct 28, 2019

23 votes

4 answers

11

GATE CSE 2018 | Question: 9
The following are some events that occur after a device controller issues an interrupt while process $L$ is under execution. P. The processor pushes the process status of $L$ onto the control stack Q. The processor finishes the execution of the ... based on the interrupt Which of the following is the correct order in which the events above occur? QPTRS PTRSQ TRPQS QTPRS

The following are some events that occur after a device controller issues an interrupt while process $L$ is under execution.P. The processor pushes the process status of ...

gatecse

10.6k views

gatecse asked Feb 14, 2018

0 votes

1 answer

12

Both internal and software interrupts are same ? Example : system call
Both internal and software caused by executing the program instructions . So both are same ?

Both internal and software caused by executing the program instructions . So both are same ?

its_vv

970 views

its_vv asked Jul 1, 2022

11 votes

1 answer

13

GATE CSE 2020 | Question: 3
Consider the following statements. Daisy chaining is used to assign priorities in attending interrupts. When a device raises a vectored interrupt, the CPU does polling to identify the source of interrupt. In polling, the CPU periodically checks the status bits to know if any ... . Which of the above statements is/are TRUE? Ⅰ and Ⅱ only Ⅰ and Ⅳ only Ⅰ and Ⅲ only Ⅲ only

Consider the following statements.Daisy chaining is used to assign priorities in attending interrupts.When a device raises a vectored interrupt, the CPU does polling to i...

Arjun

8.7k views

Arjun asked Feb 12, 2020

5 votes

4 answers

14

Interrupt
GATE -2009 A CPU generally handles an interrupt by executing an interrupt service routine As soon as an interrupt is raised. By checking the interrupt register at the end of fetch cycle. By checking the interrupt register after finishing the execution of the ... am having confusion between option A and C... For hardware interrupt option A is suitable and for software interrupt option C

GATE -2009 A CPU generally handles an interrupt by executing an interrupt service routineAs soon as an interrupt is raised.By checking the interrupt register at the end o...

#Rahul

2.8k views

#Rahul asked Oct 25, 2017

28 votes

4 answers

15

GATE CSE 1998 | Question: 1.18
Which of the following devices should get higher priority in assigning interrupts? Hard disk Printer Keyboard Floppy disk

Which of the following devices should get higher priority in assigning interrupts?Hard diskPrinterKeyboardFloppy disk

Kathleen

12.4k views

Kathleen asked Sep 25, 2014

3 votes

2 answers

16

UGC NET CSE | December 2015 | Part 3 | Question: 6
A CPU handles interrupt by executing interrput service subroutine ____ by checking interrupt register after execution of each instruction by checking interrupt register at the end of the fetch cycle whenever an interrupt is registered by checking interrupt register at regular time interval

A CPU handles interrupt by executing interrput service subroutine ____by checking interrupt register after execution of each instructionby checking interrupt register a...

go_editor

1.2k views

go_editor asked Aug 9, 2016

35 votes

5 answers

17

GATE CSE 2007 | Question: 72
Consider the following program segment. Here $\text{R1, R2}$ and $\text{R3}$ ... is word addressable. After the execution of this program, the content of memory location $2010$ is: $100$ $101$ $102$ $110$

Consider the following program segment. Here $\text{R1, R2}$ and $\text{R3}$ are the general purpose registers.$$\small \begin{array}{|c|l|l||c|} \hline & \text {Instruct...

go_editor

9.5k views

go_editor asked Apr 23, 2016

4 votes

4 answers

18

Interrupt I/O
Consider a system employing interrupt driven input/output for a particular device that transfers data at an average of 16 KB/s on a continuous basis. Assume that interrupt processing takes 50 μsec (i.e., the jump to the interrupt service routine (ISR), ... of processor time is consumed by this input/output device if it interrupt for every byte is _______ (Upto 3 decimal places).

Consider a system employing interrupt driven input/output for a particular device that transfers data at an average of 16 KB/s on a continuous basis. Assume that interrup...

Pankaj Joshi

6.7k views

Pankaj Joshi asked Feb 2, 2017

1 votes

1 answer

19

Vectored I/O

Na462

856 views

Na462 asked Sep 24, 2018

19 votes

3 answers

20

GATE CSE 1995 | Question: 1.3
In a vectored interrupt: The branch address is assigned to a fixed location in memory The interrupting source supplies the branch information to the processor through an interrupt vector The branch address is obtained from a register in the processor None of the above

In a vectored interrupt:The branch address is assigned to a fixed location in memoryThe interrupting source supplies the branch information to the processor through an in...

Kathleen

14.7k views

Kathleen asked Oct 8, 2014

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