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Search results for virtual
276
votes
14
answers
1
GATE CSE 2008 | Question: 67
A processor uses $36$ bit physical address and $32$ bit virtual addresses, with a page frame size of $4$ Kbytes. Each page table entry is of size $4$ bytes. A three level page table is used for virtual to physical address translation, where the virtual address is used as ... tables are respectively $\text{20,20,20}$ $\text{24,24,24}$ $\text{24,24,20}$ $\text{25,25,24}$
A processor uses $36$ bit physical address and $32$ bit virtual addresses, with a page frame size of $4$ Kbytes. Each page table entry is of size $4$ bytes. A three level...
Kathleen
75.7k
views
Kathleen
asked
Sep 12, 2014
Operating System
gatecse-2008
operating-system
virtual-memory
normal
+
–
129
votes
19
answers
2
GATE CSE 2004 | Question: 47
Consider a system with a two-level paging scheme in which a regular memory access takes $150$ $nanoseconds$, and servicing a page fault takes $8$ $milliseconds$. An average instruction takes $100$ nanoseconds of CPU time, and two memory accesses. ... execution time? $\text{645 nanoseconds}$ $\text{1050 nanoseconds}$ $\text{1215 nanoseconds}$ $\text{1230 nanoseconds}$
Consider a system with a two-level paging scheme in which a regular memory access takes $150$ $nanoseconds$, and servicing a page fault takes $8$ $milliseconds$. An avera...
gatecse
62.9k
views
gatecse
asked
Sep 5, 2014
CO and Architecture
gatecse-2004
co-and-architecture
virtual-memory
normal
+
–
49
votes
4
answers
3
GATE CSE 2001 | Question: 2.21
Consider a machine with $64$ MB physical memory and a $32$-bit virtual address space. If the page size s $4$ KB, what is the approximate size of the page table? $\text{16 MB}$ $\text{8 MB}$ $\text{2 MB}$ $\text{24 MB}$
Consider a machine with $64$ MB physical memory and a $32$-bit virtual address space. If the page size s $4$ KB, what is the approximate size of the page table?$\text{16 ...
Kathleen
65.3k
views
Kathleen
asked
Sep 14, 2014
Operating System
gatecse-2001
operating-system
virtual-memory
normal
+
–
121
votes
15
answers
4
GATE CSE 2003 | Question: 78
A processor uses $2-level$ page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both $32$ bits wide. The memory is byte addressable. For virtual to physical address translation, the ... virtual address is approximately (to the nearest $0.5$ ns) $1.5$ ns $2$ ns $3$ ns $4$ ns
A processor uses $2-level$ page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addres...
gatecse
46.6k
views
gatecse
asked
Sep 15, 2014
Operating System
gatecse-2003
operating-system
normal
virtual-memory
+
–
106
votes
7
answers
5
GATE CSE 2013 | Question: 52
A computer uses $46\text{-bit}$ virtual address, $32\text{-bit}$ physical address, and a three-level paged page table organization. The page table base register stores the base address of the first-level table $\text{(T1)}$ ... is $64$ bytes. What is the size of a page in $\textsf{KB}$ in this computer? $2$ $4$ $8$ $16$
A computer uses $46\text{-bit}$ virtual address, $32\text{-bit}$ physical address, and a three–level paged page table organization. The page table base register stores ...
kanikool
37.1k
views
kanikool
asked
Sep 10, 2014
Operating System
gatecse-2013
operating-system
virtual-memory
normal
+
–
51
votes
10
answers
6
GATE CSE 2020 | Question: 53
Consider a paging system that uses $1$-level page table residing in main memory and a $\textsf{TLB}$ for address translation. Each main memory access takes $100$ ns and $\textsf{TLB}$ lookup takes $20$ ns. Each page transfer to/from the disk ... $1$ decimal places) is ___________
Consider a paging system that uses $1$-level page table residing in main memory and a $\textsf{TLB}$ for address translation. Each main memory access takes $100$ ns and $...
Arjun
45.0k
views
Arjun
asked
Feb 12, 2020
Operating System
gatecse-2020
numerical-answers
operating-system
virtual-memory
2-marks
+
–
58
votes
4
answers
7
GATE CSE 2013 | Question: 53
A computer uses $46\text{-bit}$ virtual address, $32\text{-bit}$ physical address, and a three-level paged page table organization. The page table base register stores the base address of the first-level table $\text{(T1)},$ which occupies exactly one ... to guarantee that no two synonyms map to different sets in the processor cache of this computer? $2$ $4$ $8$ $16$
A computer uses $46\text{-bit}$ virtual address, $32\text{-bit}$ physical address, and a three–level paged page table organization. The page table base register stores ...
go_editor
30.1k
views
go_editor
asked
Apr 21, 2016
Operating System
gatecse-2013
normal
operating-system
virtual-memory
+
–
83
votes
6
answers
8
GATE CSE 2003 | Question: 79
A processor uses $\text{2-level}$ page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both $32$ bits wide. The memory is byte addressable. For virtual to physical address translation, ... tables of this process is $\text{8 KB}$ $\text{12 KB}$ $\text{16 KB}$ $\text{20 KB}$
A processor uses $\text{2-level}$ page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical...
go_editor
23.6k
views
go_editor
asked
Apr 24, 2016
Operating System
gatecse-2003
operating-system
normal
virtual-memory
+
–
46
votes
3
answers
9
GATE CSE 2006 | Question: 62, ISRO2016-50
A CPU generates $32$-bit virtual addresses. The page size is $4$ KB. The processor has a translation look-aside buffer (TLB) which can hold a total of $128$ page table entries and is $4$-way set associative. The minimum size of the TLB tag is: $\text{11 bits}$ $\text{13 bits}$ $\text{15 bits}$ $\text{20 bits}$
A CPU generates $32$-bit virtual addresses. The page size is $4$ KB. The processor has a translation look-aside buffer (TLB) which can hold a total of $128$ page table en...
Rucha Shelke
25.7k
views
Rucha Shelke
asked
Sep 26, 2014
Operating System
gatecse-2006
operating-system
virtual-memory
normal
isro2016
+
–
47
votes
9
answers
10
GATE CSE 1998 | Question: 2.18, UGCNET-June2012-III: 48
If an instruction takes $i$ microseconds and a page fault takes an additional $j$ microseconds, the effective instruction time if on the average a page fault occurs every $k$ instruction is: $i + \dfrac{j}{k}$ $i +(j\times k)$ $\dfrac{i+j}{k}$ $({i+j})\times {k}$
If an instruction takes $i$ microseconds and a page fault takes an additional $j$ microseconds, the effective instruction time if on the average a page fault occurs every...
Kathleen
19.2k
views
Kathleen
asked
Sep 25, 2014
Operating System
gate1998
operating-system
virtual-memory
easy
ugcnetcse-june2012-paper3
+
–
66
votes
4
answers
11
GATE CSE 2015 Set 2 | Question: 47
A computer system implements $8\;\text{kilobyte}$ pages and a $32\text{-bit}$ physical address space. Each page table entry contains a valid bit, a dirty bit, three permission bits, and the translation. If the maximum size of the page table of a process is $24\;\text{megabytes}$, the length of the virtual address supported by the system is _______ bits.
A computer system implements $8\;\text{kilobyte}$ pages and a $32\text{-bit}$ physical address space. Each page table entry contains a valid bit, a dirty bit, three permi...
go_editor
18.9k
views
go_editor
asked
Feb 13, 2015
Operating System
gatecse-2015-set2
operating-system
virtual-memory
normal
numerical-answers
+
–
66
votes
9
answers
12
GATE CSE 2004 | Question: 21, ISRO2007-44
The minimum number of page frames that must be allocated to a running process in a virtual memory environment is determined by the instruction set architecture page size number of processes in memory physical memory size
The minimum number of page frames that must be allocated to a running process in a virtual memory environment is determined bythe instruction set architecturepage sizenum...
Kathleen
23.7k
views
Kathleen
asked
Sep 18, 2014
Operating System
gatecse-2004
operating-system
virtual-memory
page-replacement
normal
isro2007
+
–
51
votes
7
answers
13
GATE CSE 2008 | Question: 38
In an instruction execution pipeline, the earliest that the data TLB (Translation Lookaside Buffer) can be accessed is: before effective address calculation has started during effective address calculation after effective address calculation has completed after data cache lookup has completed
In an instruction execution pipeline, the earliest that the data TLB (Translation Lookaside Buffer) can be accessed is:before effective address calculation has starteddur...
Kathleen
19.1k
views
Kathleen
asked
Sep 12, 2014
CO and Architecture
gatecse-2008
co-and-architecture
virtual-memory
normal
+
–
46
votes
4
answers
14
GATE CSE 1999 | Question: 19
A certain computer system has the segmented paging architecture for virtual memory. The memory is byte addressable. Both virtual and physical address spaces contain $2^{16}$ bytes each. The virtual address space is divided into $8$ non-overlapping equal ... in page table entry for storing the aging information for the page? Assume that the page size is $512$ bytes.
A certain computer system has the segmented paging architecture for virtual memory. The memory is byte addressable. Both virtual and physical address spaces contain $2^{1...
Kathleen
25.1k
views
Kathleen
asked
Sep 23, 2014
Operating System
gate1999
operating-system
virtual-memory
normal
descriptive
+
–
40
votes
5
answers
15
GATE CSE 1995 | Question: 1.7
In a paged segmented scheme of memory management, the segment table itself must have a page table because The segment table is often too large to fit in one page Each segment is spread over a number of pages Segment tables point to page tables and not to the physical locations of the segment The processor’s description base register points to a page table
In a paged segmented scheme of memory management, the segment table itself must have a page table becauseThe segment table is often too large to fit in one pageEach segme...
Kathleen
14.9k
views
Kathleen
asked
Oct 8, 2014
Operating System
gate1995
operating-system
virtual-memory
normal
+
–
38
votes
3
answers
16
GATE CSE 2014 Set 3 | Question: 33
Consider a paging hardware with a $TLB$. Assume that the entire page table and all the pages are in the physical memory. It takes $10$ milliseconds to search the $TLB$ and $80$ milliseconds to access the physical memory. If the $TLB$ hit ratio is $0.6$, the effective memory access time (in milliseconds) is _________.
Consider a paging hardware with a $TLB$. Assume that the entire page table and all the pages are in the physical memory. It takes $10$ milliseconds to search the $TLB$ an...
go_editor
15.8k
views
go_editor
asked
Sep 28, 2014
Operating System
gatecse-2014-set3
operating-system
virtual-memory
numerical-answers
normal
+
–
65
votes
6
answers
17
GATE CSE 2006 | Question: 63, UGCNET-June2012-III: 45
A computer system supports $32$-bit virtual addresses as well as $32$-bit physical addresses. Since the virtual address space is of the same size as the physical address space, the operating system designers decide to ... more efficient now Hardware support for memory management is no longer needed CPU scheduling can be made more efficient now
A computer system supports $32$-bit virtual addresses as well as $32$-bit physical addresses. Since the virtual address space is of the same size as the physical address ...
Rucha Shelke
25.6k
views
Rucha Shelke
asked
Sep 26, 2014
Operating System
gatecse-2006
operating-system
virtual-memory
normal
ugcnetcse-june2012-paper3
+
–
56
votes
7
answers
18
GATE CSE 1990 | Question: 7-b
In a two-level virtual memory, the memory access time for main memory, $t_{M}=10^{-8}$ sec, and the memory access time for the secondary memory, $t_D=10^{-3}$ sec. What must be the hit ratio, $H$ such that the access efficiency is within $80$ percent of its maximum value?
In a two-level virtual memory, the memory access time for main memory, $t_{M}=10^{-8}$ sec, and the memory access time for the secondary memory, $t_D=10^{-3}$ sec. What m...
makhdoom ghaya
18.9k
views
makhdoom ghaya
asked
Nov 23, 2016
Operating System
gate1990
descriptive
operating-system
virtual-memory
+
–
63
votes
4
answers
19
GATE CSE 2019 | Question: 33
Assume that in a certain computer, the virtual addresses are $64$ bits long and the physical addresses are $48$ bits long. The memory is word addressible. The page size is $8$ kB and the word size is $4$ bytes. The Translation Look-aside Buffer (TLB) in the address translation path ... TLB miss? $16 \times 2^{10}$ $256 \times 2^{10}$ $4 \times 2^{20}$ $8 \times 2^{20}$
Assume that in a certain computer, the virtual addresses are $64$ bits long and the physical addresses are $48$ bits long. The memory is word addressible. The page size i...
Arjun
21.4k
views
Arjun
asked
Feb 7, 2019
Operating System
gatecse-2019
operating-system
virtual-memory
2-marks
+
–
44
votes
4
answers
20
GATE IT 2007 | Question: 12
The address sequence generated by tracing a particular program executing in a pure demand paging system with $100$ bytes per page is $\text{0100, 0200, 0430, 0499, 0510, 0530, 0560, 0120, 0220, 0240, 0260, 0320, 0410.}$ Suppose that the memory can store only one page and ... to $\text{x + 99}$ are loaded on to the memory. How many page faults will occur? $0$ $4$ $7$ $8$
The address sequence generated by tracing a particular program executing in a pure demand paging system with $100$ bytes per page is$\text{0100, 0200, 0430, 0499, 0510, 0...
Ishrat Jahan
14.9k
views
Ishrat Jahan
asked
Oct 29, 2014
Operating System
gateit-2007
operating-system
virtual-memory
page-replacement
normal
+
–
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