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Recent questions tagged addressing-modes
2
votes
0
answers
31
Applied Test Series
An instruction is stored at location 300 with its address field at location 301. The address field has the value 400. A processor register R1 contains the number 200. Evaluate effective address if the addressing mode of the instruction is Index with R1 as the index register.
An instruction is stored at location 300 with its address field at location 301. The address field has the value 400. A processor register R1 contains the number 200. Eva...
LRU
898
views
LRU
asked
Oct 24, 2021
CO and Architecture
test-series
computer
co-and-architecture
addressing-modes
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1
votes
1
answer
32
NIELIT Scientific Assistant A 2020 November: 117
In the following addressing mode, which of them performs better for accessing, array? Register addressing mode Direct addressing mode Displacement addressing mode Index addressing mode
In the following addressing mode, which of them performs better for accessing, array?Register addressing modeDirect addressing modeDisplacement addressing modeIndex addre...
gatecse
420
views
gatecse
asked
Dec 9, 2020
CO and Architecture
nielit-sta-2020
co-and-architecture
addressing-modes
easy
+
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4
votes
1
answer
33
GATE Overflow Test Series | Computer Organization and Architecture | Test 1 | Question: 1
The correct sequence of steps involved in the execution of the instruction LOAD R1, X(R2) are Fetch instruction and increment PC. Compute sum [R1] + [R2] Decode instruction to determine operation. Keep quiet (No memory access) Add immediate value to the ... $a,c,e,f,g$ $a,b,c,d,e$ $a,b,e,f,h$ $a,e,f,g,h$
The correct sequence of steps involved in the execution of the instruction LOAD R1, X(R2) areFetch instruction and increment PC.Compute sum [R1] + [R2]Decode instruction ...
gatecse
228
views
gatecse
asked
Aug 3, 2020
CO and Architecture
go2025-coa-1
normal
addressing-modes
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3
votes
1
answer
34
GATE Overflow Test Series | Computer Organization and Architecture | Test 1 | Question: 8
Consider the following Assembly code fragment ldr r0, adr_var1 @ load the memory address of var1 via label adr_var1 into r0 ldr r1, adr_var2 @ load the memory address of var2 via label ... excluding register accesses) during the execution stage when the above sequence of instructions is executed is ________
Consider the following Assembly code fragmentldr r0, adr_var1 @ load the memory address of var1 via label adr_var1 into r0 ldr r1, adr_var2 @ load the memory address of v...
gatecse
475
views
gatecse
asked
Aug 3, 2020
CO and Architecture
go2025-coa-1
numerical-answers
addressing-modes
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3
votes
5
answers
35
NIELIT 2016 MAR Scientist B - Section C: 9
A certain processor supports only the immediate and the direct addressing modes. Which of the following programming language features cannot be implemented on this processor? Pointers. Arrays. Records. All of these.
A certain processor supports only the immediate and the direct addressing modes. Which of the following programming language features cannot be implemented on this proces...
admin
1.8k
views
admin
asked
Mar 31, 2020
CO and Architecture
nielit2016mar-scientistb
co-and-architecture
addressing-modes
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1
votes
3
answers
36
NIELIT 2016 DEC Scientist B (IT) - Section B: 55
The example of implied addressing is Stack addressing Indirect addressing Immediate addressing None of the above
The example of implied addressing isStack addressingIndirect addressingImmediate addressingNone of the above
admin
2.8k
views
admin
asked
Mar 31, 2020
CO and Architecture
nielit2016dec-scientistb-it
co-and-architecture
addressing-modes
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1
votes
2
answers
37
NIELIT 2016 DEC Scientist B (CS) - Section B: 53
The addressing mode used in an instruction of the form $ADD\:X\:Y$, is Direct Absolute Indirect Indexed
The addressing mode used in an instruction of the form $ADD\:X\:Y$, isDirectAbsoluteIndirectIndexed
admin
4.6k
views
admin
asked
Mar 31, 2020
CO and Architecture
nielit2016dec-scientistb-cs
co-and-architecture
addressing-modes
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1
votes
3
answers
38
NIELIT 2017 DEC Scientist B - Section B: 40
Which of the following is/are not features of RISC processor? Large number of addressing modes. Uniform instruction set. (i) Only (ii) Only Both (i) and (ii) None of the options
Which of the following is/are not features of RISC processor?Large number of addressing modes.Uniform instruction set.(i) Only(ii) OnlyBoth (i) and (ii)None of the option...
admin
4.5k
views
admin
asked
Mar 30, 2020
CO and Architecture
nielit2017dec-scientistb
co-and-architecture
addressing-modes
instruction-format
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2
votes
4
answers
39
NIELIT 2017 DEC Scientist B - Section B: 47
INCA(Increase register A by $1$) is an example of which of the following addressing mode? Immediate addressing Indirect addressing Implied addressing Relative addressing
INCA(Increase register A by $1$) is an example of which of the following addressing mode?Immediate addressingIndirect addressingImplied addressingRelative addressing
admin
2.6k
views
admin
asked
Mar 30, 2020
CO and Architecture
nielit2017dec-scientistb
co-and-architecture
addressing-modes
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1
votes
2
answers
40
NIELIT 2017 DEC Scientist B - Section B: 59
A two-word instruction is stored in a location $A$. The operand part of instruction holds $B$. If the addressing mode is relative, the operand is available in location $A+B+2$ $A+B+1$ $B+1$ $A+B$
A two-word instruction is stored in a location $A$. The operand part of instruction holds $B$. If the addressing mode is relative, the operand is available in location$A+...
admin
1.6k
views
admin
asked
Mar 30, 2020
CO and Architecture
nielit2017dec-scientistb
co-and-architecture
addressing-modes
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0
votes
3
answers
41
UGC NET CSE | January 2017 | Part 3 | Question: 4
Match the following : ... $\text{a-iv, b-ii, c-i, d-iii}$ $\text{a-iv, b-iii, c-ii, d-i}$
Match the following :$\begin{array}{clcl} & {\textbf{Addressing Mode}} & {} & {\textbf{Location of operand}} \\ \text{a.} & \text{Implied} & \text{i.} & \text{Registe...
go_editor
1.6k
views
go_editor
asked
Mar 24, 2020
CO and Architecture
ugcnetcse-jan2017-paper3
co-and-architecture
addressing-modes
match-the-following
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4
votes
5
answers
42
ISRO2020-15
A stack organized computer is characterised by instructions with indirect addressing direct addressing zero addressing index addressing
A stack organized computer is characterised by instructions withindirect addressingdirect addressingzero addressingindex addressing
Satbir
4.3k
views
Satbir
asked
Jan 13, 2020
CO and Architecture
isro-2020
co-and-architecture
addressing-modes
normal
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2
votes
1
answer
43
ISRO2020-3
Which of the following affects the processing power assuming they do not influence each other Data bus capability Address scheme Clock speed $3$ only $1$ and $3$ only $2$ and $3$ only $1,2$ and $3$
Which of the following affects the processing power assuming they do not influence each otherData bus capabilityAddress schemeClock speed$3$ only$1$ and $3$ only$2$ and $...
Satbir
3.1k
views
Satbir
asked
Jan 13, 2020
CO and Architecture
isro-2020
co-and-architecture
addressing-modes
normal
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–
6
votes
4
answers
44
ISRO2020-1
The immediate addressing mode can be used for Loading internal registers with initial values Perform arithmetic or logical operation on data contained in instructions Which of the following is true? Only $1$ Only $2$ Both $1$ and $2$ Immediate mode refers to data in cache
The immediate addressing mode can be used forLoading internal registers with initial valuesPerform arithmetic or logical operation on data contained in instructionsWhich ...
Satbir
4.0k
views
Satbir
asked
Jan 13, 2020
CO and Architecture
isro-2020
co-and-architecture
normal
addressing-modes
+
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7
votes
2
answers
45
ISRO2020-8
Consider a $32$- bit processor which supports $70$ instructions. Each instruction is $32$ bit long and has $4$ fields namely opcode, two register identifiers and an immediate operand of unsigned integer type. Maximum value of the immediate operand that can be supported by the processor is $8191$. How many registers the processor has? $32$ $64$ $128$ $16$
Consider a $32$- bit processor which supports $70$ instructions. Each instruction is $32$ bit long and has $4$ fields namely opcode, two register identifiers and an immed...
Satbir
3.8k
views
Satbir
asked
Jan 13, 2020
CO and Architecture
isro-2020
co-and-architecture
addressing-modes
normal
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3
votes
3
answers
46
UGC NET CSE | June 2019 | Part 2 | Question: 11
Which type of addressing mode, less number of memory references are required? Immediate Implied Register Indexed
Which type of addressing mode, less number of memory references are required?ImmediateImpliedRegisterIndexed
Arjun
6.4k
views
Arjun
asked
Jul 2, 2019
CO and Architecture
ugcnetcse-june2019-paper2
co-and-architecture
addressing-modes
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0
votes
2
answers
47
machine instructions and addressing modes
A digital computer has memory unit with $24$ bits word.The instruction set consists of $150$ different operations. All instructions have an operation code part and an address part. Each instruction is stored in one word of memory. $Q1$ How many bits are needed for the OP-CODE and ... $2^{16}, 2^{24}$ $2^{16},2^{24}-1$ $\textrm{None of these}$
A digital computer has memory unit with $24$ bits word.The instruction set consists of $150$ different operations. All instructions have an operation code part and an add...
Gitika Babbar
1.6k
views
Gitika Babbar
asked
May 24, 2019
CO and Architecture
co-and-architecture
addressing-modes
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0
votes
0
answers
48
selfdoubt
Show how to do the following statement c = a[2] + b[0] a) using register direct, imm, register indirect b) using register direct, imm, absolute addressing c) using register direct, imm, register indirect with displacement
Show how to do the following statement c = a + b[0]a) using register direct, imm, register indirectb) using register direct, imm, absolute addressingc) using register di...
manisha11
323
views
manisha11
asked
Mar 12, 2019
CO and Architecture
co-and-architecture
addressing-modes
register-allocation
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0
votes
0
answers
49
Self doubt
please arrange them in increasing order of speed: Relative addressing , Absolute addressing , Register addressing , Register Indirect addressing , Indirect addressing , Base addressing , indexed addressing
please arrange them in increasing order of speed:Relative addressing , Absolute addressing , Register addressing , Register Indirect addressing , Indirect addressing , Ba...
iamdeepakji
304
views
iamdeepakji
asked
Jan 27, 2019
CO and Architecture
co-and-architecture
addressing-modes
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–
0
votes
1
answer
50
Self doubt
Can anyone please explain in simple terms indexed, relative and base register addressing modes?
Can anyone please explain in simple terms indexed, relative and base register addressing modes?
subho16
511
views
subho16
asked
Jan 19, 2019
CO and Architecture
addressing-modes
co-and-architecture
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0
votes
0
answers
51
ME- CBT1
Chaitrasj
641
views
Chaitrasj
asked
Jan 14, 2019
CO and Architecture
co-and-architecture
addressing-modes
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–
1
votes
1
answer
52
What is mean by "Index Value" in Indexed Addressing Mode?
If someone mentioned "index value" in indexed addressing mode then which value is it referring; the value of index register or the constant value? It should be value of index register, isn't it? But from the given snippet it seems that they are referring constant value Please clarify Thank You
If someone mentioned "index value" in indexed addressing mode then which value is it referring; the value of index register or the constant value?It should be value of in...
newbie
968
views
newbie
asked
Jan 7, 2019
CO and Architecture
co-and-architecture
addressing-modes
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–
0
votes
1
answer
53
UPPCL AE 2018:45
In which of the following cases, a process executing in user mode requires an entry into the $\text{OS}$ mode? Decrementing an unsigned integer value stored in a register beyond zero Adding values of two registers using $\textsf{ADD}$ instruction Executing $\textsf{printf} ()$ Accessing a general purpose register
In which of the following cases, a process executing in user mode requires an entry into the $\text{OS}$ mode?Decrementing an unsigned integer value stored in a register ...
admin
295
views
admin
asked
Jan 5, 2019
CO and Architecture
uppcl2018
co-and-architecture
addressing-modes
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1
votes
1
answer
54
Indirect index addressing mode
I know about indirect addressing mode , Index addressing mode but do not know about Indirect index addressing mode ? in one solution of a question they told that Indirect index addressing mode does not add some constant value (base address etc ) while calculating the effective address i did not found it on google etc explain Indirect index addressing mode
I know about indirect addressing mode , Index addressing modebut do not know about Indirect index addressing mode ?in one solution of a question they told that Indirect...
Gurdeep Saini
819
views
Gurdeep Saini
asked
Jan 4, 2019
CO and Architecture
co-and-architecture
addressing-modes
+
–
0
votes
3
answers
55
MadeEasy Test Series: CO & Architecture - Addressing Modes
The Data transfer instruction size is $64-bit$ ALU, ALU operation instruction size is $32-bit$ and branch instruction size is $16-bit$. Assume program has been loaded in the memory starting from address 3000 decimal. If an ... executing, PC value will be 3030, but given answer is 3028 Previous Q: https://gateoverflow.in/1058/gate2004-63
The Data transfer instruction size is $64-bit$ ALU, ALU operation instruction size is $32-bit$ and branch instruction size is $16-bit$. Assume program has been loaded in ...
Learner_jai
1.6k
views
Learner_jai
asked
Dec 27, 2018
CO and Architecture
co-and-architecture
made-easy-test-series
addressing-modes
+
–
1
votes
0
answers
56
Base register AM
Assume that the base register contains $32856$. The program counter is currently at $25687$ memory location. What is the branch address if the address field of jump instruction contains $-30$ in the address field and the instruction is designed in base register addressing mode? Is it evaluated with register location or pc location?
Assume that the base register contains $32856$. The program counter is currently at $25687$ memory location. What is the branch address if the address field of jump instr...
srestha
564
views
srestha
asked
Dec 25, 2018
CO and Architecture
co-and-architecture
addressing-modes
+
–
2
votes
1
answer
57
Testbook Test Series: CO & Architecture - Addressing Modes
A PC-related mode branch instruction is $8$Byte long. The address of the instruction,in decimal, is $548321.$Find the branch target address if the signed displacement in the instruction is $-29?$
A PC-related mode branch instruction is $8$Byte long. The address of the instruction,in decimal, is $548321.$Find the branch target address if the signed displacement in ...
Lakshman Bhaiya
858
views
Lakshman Bhaiya
asked
Dec 23, 2018
CO and Architecture
co-and-architecture
testbook-test-series
addressing-modes
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–
0
votes
0
answers
58
Testbook subject test
what is the meaning of assertion.I know PC requires 1 memory access but they said 2.
what is the meaning of assertion.I know PC requires 1 memory access but they said 2.
Mayank Gupta 3
192
views
Mayank Gupta 3
asked
Dec 15, 2018
CO and Architecture
co-and-architecture
addressing-modes
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–
0
votes
1
answer
59
Addressing mode
Solution please
Solution please
twin_123
628
views
twin_123
asked
Dec 12, 2018
CO and Architecture
co-and-architecture
addressing-modes
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–
1
votes
3
answers
60
NIELIT 2018-82
Identify the true statement from the given statements. Program relocation at run time requires transfer complete block to some memory locations requires both base address and relative address requires only absolute address $1$ $1$ and $2$ $1$ , $2$ and $3$ $1$ and $3$
Identify the true statement from the given statements. Program relocation at run timerequires transfer complete block to some memory locationsrequires both base address a...
Arjun
2.0k
views
Arjun
asked
Dec 7, 2018
CO and Architecture
nielit-2018
co-and-architecture
addressing-modes
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