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A Simple Illustration
Cache Memory
Recent questions tagged cache-memory
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211
cache memory
A two-way set-associative cache memory uses blocks of four words. The cache can accommodate a total of 2048 words from the main memory. The main memory size is 32 x 128K. What is the word length of cache memory? (1) 39 bits (2) 14 bits (3) 69 bits (4) 78 bits
A two-way set-associative cache memory uses blocks of four words. The cache can accommodate a total of 2048 words from the main memory. The main memory size is 32 x 128K....
saurav raghaw
383
views
saurav raghaw
asked
Dec 27, 2018
CO and Architecture
co-and-architecture
cache-memory
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1
answer
212
Ace Test Series: CO & Architecture - Cache Memory Tag Size
The cache can hold 64 KB .data is transferred between main memory and cache in blocks of 4 bytes each.the main memory consist of 16 M Bytes . if the cache memory is 16-way set associative,Then the hexa decimal main memory address AAAAAA is mapped into which cache set?
The cache can hold 64 KB .data is transferred between main memory and cache in blocks of 4 bytes each.the main memory consist of 16 M Bytes . if the cache memory is 16-wa...
Amar Khade
828
views
Amar Khade
asked
Dec 27, 2018
CO and Architecture
cache-memory
co-and-architecture
ace-test-series
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1
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213
Miss Penalty
Suppose there are $2$ level cache. If there are $L_{1}$ and $L_{2}$ are $2$ level cache, if both have some miss rate, then still why we need miss penalty for cache in both levels?
Suppose there are $2$ level cache. If there are $L_{1}$ and $L_{2}$ are $2$ level cache, if both have some miss rate, then still why we need miss penalty for cache in bo...
srestha
414
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srestha
asked
Dec 27, 2018
CO and Architecture
cache-memory
co-and-architecture
miss-penalty
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214
MadeEasy Test Series: CO & Architecture - Cache Memory
Consider a computer system has a main memory consisting of $1 \text{ M } 16 \ bit$ words. It also has a $4\text{ K-word}$ cache organized in the block set associative manner, with $4$ blocks per set and $64$ words per block. What is the number of bits in ... $10, 5, 6$ bits $10, 4, 7$ bits $11, 4, 7$ bits I am getting an answer of $10, 4, 6$.
Consider a computer system has a main memory consisting of $1 \text{ M } 16 \ bit$ words. It also has a $4\text{ K-word}$ cache organized in the block set associative man...
zeeshanmohnavi
385
views
zeeshanmohnavi
asked
Dec 26, 2018
CO and Architecture
co-and-architecture
made-easy-test-series
cache-memory
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215
ME TEST
Consider Prof. Vamshi s writes a program given below and run on system which has 2-way set associative 16 KB data cache with 32 bytes block where each word size is 32 bits and LRU replacement policy used. If base address of array 'a is 0x0 and initially ... i] + a[1024* i]; what will be the physical memory size here?and how many bits should we assign for physical memory addressing?
Consider Prof. Vamshi‘s writes a program given below and run on system which has 2-way set associative 16 KB data cache with 32 bytes block where each word size is 32 b...
newdreamz a1-z0
457
views
newdreamz a1-z0
asked
Dec 25, 2018
CO and Architecture
computer
co-and-architecture
cache-memory
misses
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0
votes
0
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216
Calculating memory traffic in caching
Consider a cache with a line size of 64 bytes. Assume that on average 30% of the lines in the cache are dirty. A word consists of 8 bytes. Assume there is a 3% miss rate (0.97 hit ratio). Compute the amount of main memory traffic, in ... is read into cache one line at a time. However, for write back, a single word can be written from cache to main memory.
Consider a cache with a line size of 64 bytes. Assume that on average 30% of the lines in the cache are dirty. A word consists of 8 bytes. Assume there is a 3% miss rate ...
Raj Singh 1
1.1k
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Raj Singh 1
asked
Dec 24, 2018
CO and Architecture
co-and-architecture
cache-memory
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1
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217
Co Interrupt
Consider a single-level cache with an access time of 2.5 ns with a block size of 64 bytes. Main memory uses a block transfer capability that has a first word (4 bytes) access time of 50 ns and an access time of 5 ns for each word thereafter. If hit ratio of ... . Answer explain 2.5+0.05(2.5+50+15*5) which is correct? I find made easy accurate with answers for all subjects except Co.
Consider a single-level cache with an access time of 2.5 ns with a block size of 64 bytes. Main memory uses a block transfer capability that has a first word (4 bytes) ac...
Aravind Adithya 1
274
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Aravind Adithya 1
asked
Dec 24, 2018
CO and Architecture
co-and-architecture
cache-memory
effective-memory-access
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3
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0
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218
Word and byte addressable
A 4-way set-associative cache memory unit with a capacity of 32 KB is built using a block size of 16 words. The word length is 32 bits. The size of the physical address space is 4 GB. What is the number of bits tag, set, and word ... with 4bytes chunks, right? So address space is only 30 bits and not 32bits right? Which answer is correct? @arjun sir pls clarify this
A 4-way set-associative cache memory unit with a capacity of 32 KB is built using a block size of 16 words. The word length is 32 bits. The size of the physical address s...
Aravind Adithya 1
956
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Aravind Adithya 1
asked
Dec 24, 2018
CO and Architecture
co-and-architecture
cache-memory
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219
ME Test
Consider a two-level hierarchy L1 (Cache) has an accessing time of 10 nsec and main memory has accessing time of 100 nsec. Assume the hit ratio read operation is 0.75 and 40% reference are for the write operation. The average access time for the system (in nsec) if it uses write through technique is? I am getting 61 but the answer given is 67.6. please confirm the answer.
Consider a two-level hierarchy L1 (Cache) has an accessing time of 10 nsec and main memory has accessing time of 100 nsec. Assume the hit ratio read operation is 0.75 and...
Aarvi Chawla
450
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Aarvi Chawla
asked
Dec 23, 2018
CO and Architecture
co-and-architecture
cache-memory
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0
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1
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220
MadeEasy Full Length Test 2018: CO & Architecture - Cache Memory
Consider the following cache A and B .let the average access times in cache A and B is $t_A$ and $t_B$ respectively.the value of $t_A+t_B$ _(in ns) Answer is given as 30.18 ns I am getting 31.2 ns .Please verify it .
Consider the following cache A and B .let the average access times in cache A and B is $t_A$ and $t_B$ respectively.the value of $t_A+t_B$ _(in ns)Answer is given as 30.1...
Prateek Raghuvanshi
957
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Prateek Raghuvanshi
asked
Dec 22, 2018
CO and Architecture
co-and-architecture
cache-memory
made-easy-test-series
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2
votes
1
answer
221
Average memory stall
Consider a CPU contains 2000 instructions, there are 80 misses in L1 cache and 40 misses in the L2 cache. Assume miss penalty from the L2 cache to memory is 200 clock cycles, the hit time of L2 cache is 30 clock cycles, the hit ... .8 memory references per instruction, then average stall per instruction is ________. Can you please suggest the method to attempt such questions.
Consider a CPU contains 2000 instructions, there are 80 misses in L1 cache and 40 misses in the L2 cache. Assume miss penalty from the L2 cache to memory is 200 clock cy...
Shamim Ahmed
1.2k
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Shamim Ahmed
asked
Dec 22, 2018
CO and Architecture
co-and-architecture
cache-memory
stall
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2
answers
222
Memory Heirarchy Doubt
Consider a single level cache with an access time of 2.5ns with a block size of 64 bytes. Main Memory uses a block transfer capability that has a first word (4 bytes) access time of 50ns and an access time of 5ns for each word ... to consider a Strict memory hierarchy method or Parallel accessing method in Solving these types of questions? By Default which way is followed?
Consider a single level cache with an access time of 2.5ns with a block size of 64 bytes. Main Memory uses a block transfer capability that has a first word (4 bytes) acc...
Ashwani Yadav
849
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Ashwani Yadav
asked
Dec 22, 2018
CO and Architecture
co-and-architecture
effective-memory-access
cache-memory
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223
Self doubt
Assertion (A):- LRU is not applicable to direct-mapped caches. Reason (R):- A unique memory page is associated with every cache page in direct-mapped caches. Is Assertion (A) true and Reason (R) correct explanation of Assertion(A)?
Assertion (A):- LRU is not applicable to direct-mapped caches.Reason (R):- A unique memory page is associated with every cache page in direct-mapped caches.Is Assertion ...
Shadan Karim
222
views
Shadan Karim
asked
Dec 21, 2018
CO and Architecture
co-and-architecture
assertion-reason
cache-memory
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votes
2
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224
Determine Access time of system
If Cache access time is 10 ns . main memory access time is 150 ns. Cache hit rate is 99%. Determine effective access time of system.
If Cache access time is 10 ns . main memory access time is 150 ns. Cache hit rate is 99%.Determine effective access time of system.
Alina
634
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Alina
asked
Dec 21, 2018
CO and Architecture
co-and-architecture
cache-memory
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225
MadeEasy Subject Test 2019: CO & Architecture - Cache Memory
how to approcach such questions please help with all the three statements.
how to approcach such questions please help with all the three statements.
Markzuck
663
views
Markzuck
asked
Dec 21, 2018
CO and Architecture
made-easy-test-series
co-and-architecture
cache-memory
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226
MadeEasy Test Series: CO & Architecture - Cache Memory
As write through strategy is mentioned shouldnt we take SIMUALTANEOUS access formula for both read as well as write? when we will use read as parallel access formula?
As write through strategy is mentioned shouldnt we take SIMUALTANEOUS access formula for both read as well as write?when we will use read as parallel access formula?
Markzuck
704
views
Markzuck
asked
Dec 21, 2018
CO and Architecture
made-easy-test-series
co-and-architecture
cache-memory
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227
Direct Mapping
what’s the answer here ...unable to understand their solution. and also shouldn’t be the reason like this For R to be true: “ A unique cache page is associated with every main memory page in direct mapped caches. “
what’s the answer here ...unable to understand their solution.and also shouldn’t be the reason like this For R to be true: “ A unique cache page is associated with ...
Ashwani Yadav
615
views
Ashwani Yadav
asked
Dec 20, 2018
CO and Architecture
cache-memory
direct-mapping
co-and-architecture
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228
Doubt : Previous year
Question : https://gateoverflow.in/91103/me-flt-4-q-58 ( i couldn't understand the discussion so solved like this := ) (Please check where i am doing wrong ) Approach : Dont understand whether method is wrong or formula is wrong. ( default method is used i. ... solve this ? ( if penalty is mentioned then how to use it ? means when to add cache time in it and when to not )
Question : https://gateoverflow.in/91103/me-flt-4-q-58 ( i couldn't understand the discussion so solved like this := )(Please check where i am doing wrong ) Approach : ...
HeadShot
593
views
HeadShot
asked
Dec 19, 2018
CO and Architecture
co-and-architecture
cache-memory
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0
votes
0
answers
229
Calculating average access time in multi level cache
$h_1→L1$ hit ratio $h_2→L2$ hit ratio $C_1→ L1$ access time $C_2→ $Miss penalty to transfer information from L2 to L1 $M→$ Miss penalty to transfer information from main memory to L2 Average access time given in Carl Hamacher's book ... red. Is my equation correct or book's equation. Or something more is going on here, which I am unaware of?
$h_1→L1$ hit ratio $h_2→L2$ hit ratio$C_1→ L1$ access time$C_2→ $Miss penalty to transfer information from L2 to L1$M→$ Miss penalty to transfer information fro...
Raj Singh 1
1.2k
views
Raj Singh 1
asked
Dec 19, 2018
CO and Architecture
cache-memory
multilevel-cache
co-and-architecture
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0
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0
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230
Calculating cache penalty
For a system with two levels of cache, define $T_{c1}$ first-level cache access time; $T_{c2}$ second-level cache access time; $T_m$ memory access time; $H_1$ first-level cache hit ratio; $H_2$ combined first/second level cache hit ratio. Provide an equation for effective access time $T_a$ for a read operation.
For a system with two levels of cache, define $T_{c1}$ first-level cache access time; $T_{c2}$ second-level cache access time; $T_m$ memory access time; $H_1$ first-level...
Raj Singh 1
266
views
Raj Singh 1
asked
Dec 19, 2018
CO and Architecture
co-and-architecture
cache-memory
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1
votes
0
answers
231
Direct Mapping and set associative Mapping
https://gateoverflow.in/1851/gate2006-74 https://gateoverflow.in/43565/gate2006-75 can someone check this questions ? i am not getting, how without help of MULTIPLEXER or DECODER, we are searching hit/miss i mean in direct mapping, how we select lines and their respective Tags without help of Multiplexer ?
https://gateoverflow.in/1851/gate2006-74https://gateoverflow.in/43565/gate2006-75can someone check this questions ?i am not getting, how without help of MULTIPLEXER or DE...
Shaik Masthan
2.3k
views
Shaik Masthan
asked
Dec 18, 2018
CO and Architecture
cache-memory
direct-mapping
comparators
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0
votes
0
answers
232
Self Doubt
Conflict misses and inference misses reduces can be reduced by doubling the associativity of cache design? True or False with some explanation
Conflict misses and inference misses reduces can be reduced by doubling the associativity of cache design?True or False with some explanation
Shadan Karim
199
views
Shadan Karim
asked
Dec 18, 2018
CO and Architecture
co-and-architecture
cache-memory
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1
votes
0
answers
233
Set associative cache implementation
Given the following specifications for an external cache memory: four-way set associative; line size of two 16-bit words; able to accommodate a total of 4K 32-bit words from main memory; used with a 16-bit processor that issues 24-bit addresses. Show how cache interprets the processor’s addresses.
Given the following specifications for an external cache memory: four-way set associative; line size of two 16-bit words; able to accommodate a total of 4K 32-bit words f...
Raj Singh 1
1.1k
views
Raj Singh 1
asked
Dec 18, 2018
CO and Architecture
co-and-architecture
cache-memory
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0
votes
0
answers
234
TESTBOOK COA
Mayank Gupta 3
423
views
Mayank Gupta 3
asked
Dec 15, 2018
CO and Architecture
co-and-architecture
cache-memory
testbook-test-series
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0
votes
0
answers
235
Self Doubt
How to find the number of mux required in a k-way set associative cache? Please give the implementation of the same.
How to find the number of mux required in a k-way set associative cache?Please give the implementation of the same.
Vipin Rai
261
views
Vipin Rai
asked
Dec 15, 2018
CO and Architecture
co-and-architecture
cache-memory
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0
votes
2
answers
236
MadeEasy Test Series: CO & Architecture - Cache Memory
consider a CPU contains 2000 instructions, there are 80 misses in L1 cache and 40 misses in the L2 cache. Assume miss penalty from the L2 cache to memory is 200 clock cycles, the hit time of L2 cache is 30 clock cycles, the hit ... and there are 1.8 memory references per instruction, then average stall per instruction is 6.36 7.92 9.62 9.35
consider a CPU contains 2000 instructions, there are 80 misses in L1 cache and 40 misses in the L2 cache. Assume miss penalty from the L2 cache to memory is 200 clock cyc...
scarz
773
views
scarz
asked
Dec 15, 2018
CO and Architecture
made-easy-test-series
co-and-architecture
cache-memory
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0
votes
0
answers
237
Cache organisation
Do we use multiplexer in direct mapped cache ?
Do we use multiplexer in direct mapped cache ?
Mayank Gupta 3
244
views
Mayank Gupta 3
asked
Dec 14, 2018
CO and Architecture
co-and-architecture
cache-memory
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1
votes
0
answers
238
METest_COA
Consider professor vamshi writes a program given below and run on a system which has 2way set associative 16KB data cache with 32 bytes block where each word size is 32 bits and LRU replacement policy is used. and the base address of the array is $0x0$ and ... new block is accessed which causes a cache miss. Total misses=$1023+128=1151$ Please let me know If I went somewhere wrong.
Consider professor vamshi writes a program given below and run on a system which has 2way set associative 16KB data cache with 32 bytes block where each word size is 32 b...
Ayush Upadhyaya
411
views
Ayush Upadhyaya
asked
Dec 12, 2018
CO and Architecture
cache-memory
co-and-architecture
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0
votes
1
answer
239
https://gateoverflow.in/14480/formula-write-back-write-through-access-time-parallel-serial
In this question can someone plz explain to me the write back part? Why are we taking write back time only for cache misses? Why not for hits? How to know when a block is going to be replaced and when to consider write back time.
In this question can someone plz explain to me the write back part? Why are we taking write back time only for cache misses? Why not for hits? How to know when a block i...
sushmita
747
views
sushmita
asked
Dec 12, 2018
CO and Architecture
cache-memory
co-and-architecture
write-through
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0
votes
0
answers
240
General doubt.
I am unable to understand the memory access time for hierarchical and simultaneous access using write back policy even after reading from go sources. Can someone plz explain?
I am unable to understand the memory access time for hierarchical and simultaneous access using write back policy even after reading from go sources. Can someone plz expl...
sushmita
254
views
sushmita
asked
Dec 12, 2018
CO and Architecture
computer
co-and-architecture
cache-memory
effective-memory-access
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