Recent questions tagged cache-memory

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Suppose there are $2$ level cache. If there are $L_{1}$ and $L_{2}$ are $2$ level cache, if both have some miss rate, then still why we need miss penalty for cache in bo...
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If Cache access time is 10 ns . main memory access time is 150 ns. Cache hit rate is 99%.Determine effective access time of system.
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As write through strategy is mentioned shouldnt we take SIMUALTANEOUS access formula for both read as well as write?when we will use read as parallel access formula?
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Conflict misses and inference misses reduces can be reduced by doubling the associativity of cache design?True or False with some explanation
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How to find the number of mux required in a k-way set associative cache?Please give the implementation of the same.
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I am unable to understand the memory access time for hierarchical and simultaneous access using write back policy even after reading from go sources. Can someone plz expl...