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A Simple Illustration
Cache Memory
Recent questions tagged cache-memory
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61
cache memory
Consider a RISC processor with an ideal CPI, where 25% of the total instructions are LOAD and STORE instruction. Time to accessing main memory is 100 clock cycles and accessing of the cache memory required 2 clock cycles. If cache miss rate is 2%, then the effective CPI for the system with the cache is ____.
Consider a RISC processor with an ideal CPI, where 25% of the total instructions are LOAD and STORE instruction. Time to accessing main memory is 100 clock cycles and acc...
someshawasthi
354
views
someshawasthi
asked
Nov 17, 2022
CO and Architecture
cache-memory
clock-cycles
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0
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0
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62
cache memory
Consider a process where each instruction takes on average 3 cycle and there are 1.8 references to memory per instruction. A program with 50000 instruction is executed on this machine using a split cache of 32KB, obtained a 85% bit rate, 3ns bit time and 21ns miss penalty the execution time for the cache is ___ (μsec)
Consider a process where each instruction takes on average 3 cycle and there are 1.8 references to memory per instruction. A program with 50000 instruction is executed on...
someshawasthi
285
views
someshawasthi
asked
Nov 16, 2022
CO and Architecture
co-and-architecture
cache-memory
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1
votes
1
answer
63
Zeal test series
A computer system uses $16-$bit memory addresses.It has a $16KB$ cache organized in a $4-$ way set associative manner with $64 $ bytes per cache block.Assume that size of each memory word is 2B .When a program is executed ,The processor read ... .All the above addresses shown in decimal values.Assume cache is initially empty .The number of addresses hit in the cache ?
A computer system uses $16-$bit memory addresses.It has a $16KB$ cache organized in a $4-$ way set associative manner with $64 $ bytes per cache block.Assume that size of...
Kabir5454
543
views
Kabir5454
asked
Nov 1, 2022
CO and Architecture
zeal
cache-memory
numerical-answers
test-series
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2
votes
1
answer
64
cache memory
THE size of memory required at cache controller to store the metadata is 2kbyte The metadata include tag bits 1 modified bit and 1 valid bit The cache contain 1KBlocks of 32 bytes each organized as directed mapped The size of Main memory is __ Mbytes?
THE size of memory required at cache controller to store the metadata is 2kbyte The metadata include tag bits 1 modified bit and 1 valid bit The cache contain 1KBlocks of...
Vaishnavi Gadhe
478
views
Vaishnavi Gadhe
asked
Oct 25, 2022
CO and Architecture
cache-memory
numerical-answers
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2
votes
0
answers
65
Operating System: Self Doubt - Memory Management
Considering a system with Single-Level page table, with a TLB to reduce the access time of pages. A cache is also provided with the main memory. All the pages ultimately reside in MM. (assuming there's no page fault). Let, TLB Hit Ratio = x TLB Access ... for TLB miss it will be (a+c+p). But if this is true, why can't we store Page Table in a Cache?
Considering a system with Single-Level page table, with a TLB to reduce the access time of pages. A cache is also provided with the main memory. All the pages ultimately ...
DebRC
355
views
DebRC
asked
Sep 14, 2022
Operating System
memory-management
operating-system
paging
cache-memory
self-doubt
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0
votes
1
answer
66
Gate@Zeal 2022
SKMAKM
334
views
SKMAKM
asked
Sep 2, 2022
CO and Architecture
cache-memory
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1
votes
1
answer
67
Gate Zeal@ Test Series 2022
Ans is 2168 Please help someone
Ans is 2168 Please help someone
SKMAKM
250
views
SKMAKM
asked
Sep 2, 2022
CO and Architecture
cache-memory
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5
votes
1
answer
68
GO Classes Test Series 2023 | CO and Architecture | Test 3 | Question: 2
If a memory system consists of a single external cache with an access time of $20$ ns and a hit rate of $0.92,$ and a main memory with an access time of $60$ ns, what is the effective memory access time, in ns, of this system?
If a memory system consists of a single external cache with an access time of $20$ ns and a hit rate of $0.92,$ and a main memory with an access time of $60$ ns, what is ...
GO Classes
318
views
GO Classes
asked
Aug 31, 2022
CO and Architecture
goclasses2024-coa-3-weekly-quiz
numerical-answers
goclasses
co-and-architecture
cache-memory
hit-ratio
1-mark
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1
votes
1
answer
69
ISI 2021 | PCB CS | Question: 7.b
Consider a $4$-way set associative cache mapping, in which the cache blocks are grouped into sets and each set has $4$ blocks. There are $16$ cache blocks in total. The following memory block requests arrive in order when ... . Show the cache configuration (along with intermediate configurations) on meeting the above memory requirements. What is the hit ratio?
Consider a $4$-way set associative cache mapping, in which the cache blocks are grouped into sets and each set has $4$ blocks. There are $16$ cache blocks in total. The f...
admin
733
views
admin
asked
Aug 24, 2022
CO and Architecture
isi2021-pcb-cs
descriptive
co-and-architecture
cache-memory
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1
votes
1
answer
70
Zeal Test
Question : Consider a system with 20 bit physical address and direct mapped cache with 64 blocks and block size of 16 bytes To what block number does byte address 1200 mapped??
Question :Consider a system with 20 bit physical address and direct mapped cache with 64 blocks and block size of 16 bytes To what block number does byte address 1200 map...
lalitver10
699
views
lalitver10
asked
Aug 19, 2022
CO and Architecture
co-and-architecture
zeal
cache-memory
direct-mapping
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