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Recent questions tagged cisc-risc-architecture
21
votes
7
answers
1
GATE CSE 2018 | Question: 5
Consider the following processor design characteristics: Register-to-register arithmetic operations only Fixed-length instruction format Hardwired control unit Which of the characteristics above are used in the design of a RISC processor? I and II only II and III only I and III only I, II and III
Consider the following processor design characteristics:Register-to-register arithmetic operations onlyFixed-length instruction formatHardwired control unitWhich of the c...
gatecse
12.0k
views
gatecse
asked
Feb 14, 2018
CO and Architecture
gatecse-2018
co-and-architecture
cisc-risc-architecture
easy
1-mark
+
–
1
votes
1
answer
2
Test by Bikram | Mock GATE | Test 4 | Question: 28
There is an $RISC$ processor which uses pipeline technique. Within the processor, all the arithmetic instructions have the same $CPI$ (cycles per instruction). Which of the following actions would improve the execution time of an arithmetically ... and the data cache without changing the clock cycle time. II only I and III III only I and II
There is an $RISC$ processor which uses pipeline technique. Within the processor, all the arithmetic instructions have the same $CPI$ (cycles per instruction).Which of th...
Bikram
487
views
Bikram
asked
May 14, 2017
CO and Architecture
tbb-mockgate-4
co-and-architecture
cisc-risc-architecture
pipelining
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–
2
votes
2
answers
3
Q-20 (control unit design) madeEasy workBook 2015
Show below are sements of a code run on a CISC and RISC archy separately CISC RISC MOV AX,05 MOV AX,00 MOV BX,06 MOV BX,05 MUL AX,BX MOV CX,06 start:ADD AX,BX loop loop start; loop till CX=0 If the MUL instruction takes 40 clock cycles, ... 2.8 (c) The CISC code runs slower by a factor of 0.025 (d) The RISC code will run faster by a factor of 40
Show below are sements of a code run on a CISC and RISC archy separatelyCISC RISCMOV AX,05 ...
khushtak
2.2k
views
khushtak
asked
Oct 7, 2015
CO and Architecture
clock-frequency
co-and-architecture
cisc-risc-architecture
+
–
35
votes
4
answers
4
GATE CSE 1999 | Question: 2.22
The main difference(s) between a CISC and a RISC processor is/are that a RISC processor typically has fewer instructions has fewer addressing modes has more registers is easier to implement using hard-wired logic
The main difference(s) between a CISC and a RISC processor is/are that a RISC processor typicallyhas fewer instructionshas fewer addressing modeshas more registersis easi...
Kathleen
9.1k
views
Kathleen
asked
Sep 23, 2014
CO and Architecture
gate1999
co-and-architecture
normal
cisc-risc-architecture
multiple-selects
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