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Recent questions tagged decoder
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Counting number of "AND" and "OR" gates in a multiplexer and decoder. How do we approach such questions?
tishhaagrawal
286
views
tishhaagrawal
asked
Dec 4, 2023
Digital Logic
made-easy-test-series
test-series
gate-preparation
digital-logic
digital-circuits
multiplexer
decoder
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–
0
votes
0
answers
2
Madeeasy ots Digital Logic Combinational Circuits
I am confused in active low enable input and active low output?
I am confused in active low enable input and active low output?
Sajal Mallick
205
views
Sajal Mallick
asked
Nov 23, 2023
Digital Logic
digital-logic
combinational-circuit
digital-circuits
made-easy-test-series
decoder
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–
0
votes
1
answer
3
ISI2020-PCB-CS: 10
Suppose instead of a decoder with $n$ input bits ( $n$ is even) to access a memory of size $2^{n}$, one uses two decoders of input sizes $k$ bits and $(n-k)$ bits. Explain how these two decoders can be used to access the ... address decoding time. Justify your answer. Assume that the time complexity of the decoder is measured by the number of output lines of that decoder.
Suppose instead of a decoder with $n$ input bits ( $n$ is even) to access a memory of size $2^{n}$, one uses two decoders of input sizes $k$ bits and $(n-k)$ bits. Explai...
admin
383
views
admin
asked
Aug 8, 2022
Digital Logic
isi2020-pcb-cs
digital-logic
combinational-circuit
decoder
descriptive
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–
0
votes
1
answer
4
ISI2021-PCB-C10
Suppose instead of a decoder with n input bits (n is even) to access a memory of size 2^n, one uses two decoders of input sizes k bits and (n-k) bits. Explain how these two decoders can be used to access the memory of size 2^N. ... address decoding time. Justify your answer. Assume that the time complexity of the decoder is measured by the number of output lines of that decoder.
Suppose instead of a decoder with n input bits (n is even) to access a memory of size 2^n, one uses two decoders of input sizes k bits and (n-k) bits. Explain how these t...
jatin29
583
views
jatin29
asked
May 3, 2022
Digital Logic
digital-logic
decoder
isi
+
–
0
votes
1
answer
5
Made Easy Test Series
A 3 to 8 decoder is shown below: All output lines of decoder will be high when all the input I1, I2, I3 are; are high and G1 , G2 are low are high and G1 is high , G2 is low are high and G1 is low , G2 is high are high and G1 , G2 are high Please someone help to understand the logic behind this question. Why we have to disable the Decoder to make all the outputs high ?
A 3 to 8 decoder is shown below:All output lines of decoder will be high when all the input I1, I2, I3 are;are high and G1 , G2 are loware high and G1 is high , G2 is low...
Rajat Agrawal007
624
views
Rajat Agrawal007
asked
Nov 22, 2021
Digital Logic
made-easy-test-series
digital-logic
decoder
+
–
0
votes
0
answers
6
3 to 8 line Decoder (Combinational Circuit)
If F1 = ∑m(1,2,4,7) and F2 = ∑m(3,5,6,7), implement them using 3 to 8 line decoder. Comment on their logic operations.
If F1 = ∑m(1,2,4,7) and F2 = ∑m(3,5,6,7), implement them using 3 to 8 line decoder. Comment on their logic operations.
gikovi
637
views
gikovi
asked
Sep 25, 2021
Digital Logic
digital-logic
combinational-circuit
decoder
digital-circuits
+
–
1
votes
2
answers
7
GATE Overflow Test Series | Mixed Subjects | Test 2 | Question: 22
The minimum number of 2-to-4 line decoders with an enable input needed to construct a 4-to-16 line decoder without using any other logic gates is _____
The minimum number of 2-to-4 line decoders with an enable input needed to construct a 4-to-16 line decoder without using any other logic gates is _____
gatecse
98
views
gatecse
asked
Aug 30, 2020
Digital Logic
go2025-mix-2
numerical-answers
decoder
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–
17
votes
4
answers
8
GATE CSE 2020 | Question: 20
If there are $m$ input lines and $n$ output lines for a decoder that is used to uniquely address a byte addressable $1$ KB RAM, then the minimum value of $m+n$ is ________ .
If there are $m$ input lines and $n$ output lines for a decoder that is used to uniquely address a byte addressable $1$ KB RAM, then the minimum value of $m+n$ is _______...
Arjun
9.7k
views
Arjun
asked
Feb 12, 2020
Digital Logic
gatecse-2020
numerical-answers
digital-logic
decoder
1-mark
+
–
3
votes
2
answers
9
Made Easy Test Series: Digital Logic
A $3\times 8$ decoder with $2$ enable inputs is used to address $8$ block of memory. What will be the size of each memory block when addressed from a $16$ bit bus with $2$ MSB’s used to enable the decoder?
A $3\times 8$ decoder with $2$ enable inputs is used to address $8$ block of memory. What will be the size of each memory block when addressed from a $16$ bit bus with $...
srestha
1.4k
views
srestha
asked
May 15, 2019
Digital Logic
digital-logic
made-easy-test-series
decoder
+
–
1
votes
0
answers
10
Morris Mano Edition 3 Exercise 5 Question 18 (Page No. 199)
Construct a $5 \times 32 $ decoder with four $3\times8$ decoders with enable and one $ 2 \times 4$ decoder. use a block diagram also.
Construct a $5 \times 32 $ decoder with four $3\times8$ decoders with enable and one $ 2 \times 4$ decoder. use a block diagram also.
ajaysoni1924
489
views
ajaysoni1924
asked
Apr 3, 2019
Digital Logic
digital-logic
morris-mano
combinational-circuit
decoder
+
–
0
votes
0
answers
11
Morris Mano Edition 3 Exercise 5 Question 17 (Page No. 199)
Draw the logic diagram of a 2-to-4 line decoder with only NOR gates. Include an Enable input.
Draw the logic diagram of a 2-to-4 line decoder with only NOR gates. Include an Enable input.
ajaysoni1924
334
views
ajaysoni1924
asked
Apr 3, 2019
Digital Logic
digital-logic
morris-mano
combinational-circuit
decoder
+
–
0
votes
1
answer
12
DRDO 2009
The number of 2-to-4 line decoders with enable input needed to construct a 4-to-16 line decoder are?
The number of 2-to-4 line decoders with enable input needed to construct a 4-to-16 line decoder are?
Sambhrant Maurya
1.8k
views
Sambhrant Maurya
asked
Jan 3, 2019
Digital Logic
decoder
combinational-circuit
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–
0
votes
1
answer
13
Made easy theory book
Solve this.
Solve this.
Jyoti Kumari97
845
views
Jyoti Kumari97
asked
Dec 30, 2018
Digital Logic
made-easy-booklet
self-doubt
digital-logic
decoder
+
–
1
votes
1
answer
14
MadeEasy Test Series: Digital Logic - Decoder
A $3 \times 8$ decoder with two enables inputs is to be used to address 8 blocks of memory. What will be the size of each memory block when addressed from a sixteen-bit bus with two MSBs used to enable the decoder? $i)2k$ $ii)4k$ $iii)16k$ $iv) 64k$ What does “two enable inputs is to be used” mean? I am not able to visualize the circuit.
A $3 \times 8$ decoder with two enables inputs is to be used to address 8 blocks of memory. What will be the size of each memory block when addressed from a sixteen-bit ...
shreyansh jain
2.2k
views
shreyansh jain
asked
Dec 28, 2018
Digital Logic
made-easy-test-series
decoder
digital-logic
+
–
1
votes
3
answers
15
NIELIT 2018-39
A RAM chip has a capacity of $1024$ words of $8$ bits each $(1K \times 8)$. The number of $2 \times 4$ decoders with enable line needed to construct a $32 K \times 8$ RAM from $1K \times 8$ RAM is $4$ $5$ $6$ $7$
A RAM chip has a capacity of $1024$ words of $8$ bits each $(1K \times 8)$. The number of $2 \times 4$ decoders with enable line needed to construct a $32 K \times 8$ RAM...
Arjun
2.7k
views
Arjun
asked
Dec 7, 2018
Digital Logic
nielit-2018
digital-logic
combinational-circuit
decoder
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–
1
votes
2
answers
16
Decoder
Na462
1.0k
views
Na462
asked
Nov 7, 2018
CO and Architecture
rom
digital-logic
co-and-architecture
decoder
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