Register

Recent questions tagged digital-counter

0 votes
0 answers
3
GFG CSE Mock 2018 | Sequential Circuits
Consider following counters: Counter-1: Counter-2: Which of the following option is correct? Counter-1 is a three-bit "counter" which counts $0, 1, 2, 4, 5, 7, 0, ... . $ ... $0, 1, 2, 3, 5, 6, 0, ... $.
Consider following counters:Counter-1: Counter-2: Which of the following option is correct? Counter-1 is a three-bit "counter" which counts $0, 1, 2, 4, 5, 7, 0, ... . $ ...
User Avatar
0 votes
0 answers
6
madeeasy booklet
Here clr is active low that means 0 then it will clear to 0. Then (Q2.Q0)' =0 or Q2=1 and Q0=1 then clr works. Then it will contain only 1 state. Right?? But answer is different.
Here clr is active low that means 0 then it will clear to 0. Then (Q2.Q0)' =0 or Q2=1 and Q0=1 then clr works. Then it will contain only 1 state. Right?? But answer is ...
User Avatar
0 votes
0 answers
7
ripple counter
In a 4-bit binary ripple counter, for every input clock pulse (a) All the flip-flops get clocked simultaneously. (b) Only one flip-flop get clocked at a time. (c) Two of the flip-flops get clocked at a time. (d) All the above statements are false.
In a 4-bit binary ripple counter, for every input clock pulse(a) All the flip-flops get clocked simultaneously.(b) Only one flip-flop get clocked at a time.(c) Two of the...
User Avatar
0 votes
0 answers
8
self doubt
if i have given 2 flip flop clock simultaneously and 2 flip flop clock non simultaneously what is it synchronous counter or asynchronous counter ? why?
if i have given 2 flip flop clock simultaneously and 2 flip flop clock non simultaneously what is it synchronous counter or asynchronous counter ? why?
User Avatar
0 votes
1 answer
14
Made Easy Test Series Question
The frequency of the pulse at D is __________ Hz.
The frequency of the pulse at D is __________ Hz.
User Avatar
0 votes
0 answers
15
Made Easy Test Series Question
The output frequency of a decade counter that is clocked from a 50 kHz signal is _________ kHz.
The output frequency of a decade counter that is clocked from a 50 kHz signal is _________ kHz.
User Avatar
8 votes
1 answer
19
GATE Overflow Test Series | Mock GATE | Test 3 | Question: 19
Three cascaded modulus-$7$ counters have an overall modulus of $\alpha,$ and three cascaded decade counters will divide the input frequency by $\beta.$ Then the value of $\alpha + \beta = $__________
Three cascaded modulus-$7$ counters have an overall modulus of $\alpha,$ and three cascaded decade counters will divide the input frequency by $\beta.$ Then the value of ...
User Avatar
4 votes
1 answer
20
GATE Overflow Test Series | Mock GATE | Test 2 | Question: 22
A $21$-bit asynchronous binary counter is made up of twenty one flip-flops, each with a $21\;\text{ns}$ propagation delay. The total propagation delay is _________ (nanoseconds)
A $21$-bit asynchronous binary counter is made up of twenty one flip-flops, each with a $21\;\text{ns}$ propagation delay. The total propagation delay is _________ (nanos...
User Avatar
4 votes
1 answer
21
GATE Overflow Test Series | Mock GATE | Test 2 | Question: 24
A $4$-bit ripple counter and a $4$-bit synchronous counter are made using flip-flops having a propagation delay of $2021\;\text{ns}$ ... $T_{\text{ripple}} - T_{\text{synchronous}} = $____________ (in nanoseconds)
A $4$-bit ripple counter and a $4$-bit synchronous counter are made using flip-flops having a propagation delay of $2021\;\text{ns}$ each. If the worst case delay in the ...
User Avatar
Page: