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Recent questions tagged effective-memory-access
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votes
2
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1
pipelining hazard
Consider a 5-stage pipelined processor with stages - Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MA) and Write Back (WB). All stages except Memory Access takes 1 clock cycle each for all instructions. Memory access takes 3 clock cycles for instruction LOAD. How many ... (R4) ; R3 ← [4 + [R4]] I3 : SUB R5, R3, R4 ; R5 ← R3 - R4 ans is 14 bt how?
Consider a 5–stage pipelined processor with stages – Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MA) and Write Back (WB). All stages...
24aaaa23
428
views
24aaaa23
asked
Oct 3, 2023
Operating System
operating-system
pipelining
effective-memory-access
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0
votes
1
answer
2
OPERATING SYSTEM
Assuming 3-level of paging is used by a paging system and a TLB for address translation. Calculate Average memory access time if each main memory access takes 100ns and TLB access time is 10ns, page fault service time is given as 200ns and TLB hit ratio is 80% and page fault rate is 10%.
Assuming 3-level of paging is used by a paging system and a TLB for address translation. Calculate Average memory access time if each main memory access takes 100ns and T...
24aaaa23
418
views
24aaaa23
asked
Oct 2, 2023
Operating System
operating-system
paging
effective-memory-access
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0
votes
1
answer
3
Topic: Hit Ratio
The access time of a main memory is 800 ns and cache memory access time is 70 ns. The ratio of read and write requests is 7:3. The hit ratio for read access only is 80%. Calculate the hit ratio for all the memory requests (i.e. both read and write requests) if a write-through policy is used for cache updation.
The access time of a main memory is 800 ns and cache memory access time is 70 ns. The ratio of read and write requests is 7:3. The hit ratio for read access only is 80%. ...
rahulkarmakar
425
views
rahulkarmakar
asked
Jun 16, 2023
CO and Architecture
co-and-architecture
effective-memory-access
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0
votes
1
answer
4
#selfdoubt
Given values: 1-level page table Memory access time =10ms Page fault service time=20ms Page fault rate=40% what is the effective memory access time?
Given values:1-level page tableMemory access time =10msPage fault service time=20ms Page fault rate=40% what is the effective memory access time?
Dknights
321
views
Dknights
asked
Apr 25, 2023
Operating System
operating-system
effective-memory-access
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0
votes
0
answers
5
#self_doubt
which one is correct to use in exam here (1-p) is as page fault EMAT=p(m+m)+(1-p)(pfst) https://gateoverflow.in/333178/gate-cse-2020-question-53 this is a tlb question but my point is here we are adding 2 memory access in 1-level page table but in ... time so which is right? EMAT=p(m)+(1-p)(pfst) https://gateoverflow.in/401429/go-classes-test-series-2023-iiith-mock-test-2-question-94
which one is correct to use in exam here (1-p) is as page faultEMAT=p(m+m)+(1-p)(pfst)https://gateoverflow.in/333178/gate-cse-2020-question-53this is a tlb question but m...
Dknights
234
views
Dknights
asked
Apr 16, 2023
Operating System
operating-system
effective-memory-access
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2
votes
1
answer
6
What is the solution?
I think the answer must be 500200ns
I think the answer must be 500200ns
h4kr
322
views
h4kr
asked
Dec 29, 2022
Operating System
operating-system
virtual-memory
probability
effective-memory-access
made-easy-test-series
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1
votes
1
answer
7
Calculate the effective access time.
A demand paging system provides a TLB (15 ns access time), cache memory (25 ns access time), main memory (75 ns access time, NOT including the cache miss ) and 5 ms to service a page fault. The page table is found in the TLB 70% ... memory location is found in the cache 70% of the time and in main memory 20% of the time. Calculate the effective access time.
A demand paging system provides a TLB (15 ns access time), cache memory (25 ns access time), main memory (75 ns access time, NOT including the cache “miss”) and 5 ms ...
hoangminh
2.5k
views
hoangminh
asked
Nov 30, 2022
Operating System
operating-system
effective-memory-access
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1
votes
0
answers
8
Madeasy Test series
vishnu777
298
views
vishnu777
asked
Nov 23, 2022
CO and Architecture
multilevel-cache
made-easy-test-series
effective-memory-access
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0
votes
1
answer
9
Accesing time
Could you please differentiate below . Memory access time .hit time . search time ?? Arey yar some one answer this.. why so dumb
Could you please differentiate below. Memory access time.hit time. search time??Arey yar some one answer this.. why so dumb
Subbu.
188
views
Subbu.
asked
Aug 6, 2022
CO and Architecture
co-and-architecture
effective-memory-access
hit-ratio
self-doubt
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2
votes
1
answer
10
NPTEL Assignment
Consider a two-level memory hierarchy with separate instruction and data caches in level 1, and main memory in level 2. The clock cycle time in 1 ns. The miss penalty is 20 clock cycles for both read and write. 2% of the instructions are not found ... access time (including hit detection) is 1 clock cycle. The average access time of the memory hierarchy will be . nanoseconds
Consider a two-level memory hierarchy with separate instruction and data caches in level 1, and main memory in level 2. The clock cycle time in 1 ns. The miss penalty is ...
LRU
593
views
LRU
asked
Dec 4, 2021
CO and Architecture
nptel-quiz
co-and-architecture
effective-memory-access
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2
votes
1
answer
11
NPTEL Assignment
Assume that a read request takes 50 nsec on a cache miss and 5 nsec on a cache hit. While running a program, it is observed that 80% of the processor’s read requests result in a cache hit. The average read access time is ………….. nsec.
Assume that a read request takes 50 nsec on a cache miss and 5 nsec on a cache hit. While running a program, it is observed that 80% of the processor’s read requests re...
LRU
282
views
LRU
asked
Dec 4, 2021
CO and Architecture
nptel-quiz
co-and-architecture
effective-memory-access
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2
votes
2
answers
12
Applied Test Series
Consider the following memories with their miss rates and hit times Then the average memory access time is ______ (in ns)
Consider the following memories with their miss rates and hit times Then the average memory access time is ______ (in ns)
LRU
530
views
LRU
asked
Nov 5, 2021
CO and Architecture
test-series
co-and-architecture
cache-memory
effective-memory-access
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0
votes
1
answer
13
Applied Test Series
An operating system implements a single level paging. This system uses Translation Lookaside Buffer (TLB) and Physical Address Cache (PAC) as well. TLB has a hit ratio 90%. PAC has a miss ratio of 20%. Main memory access time, TLB access time and ... ns respectively. Assuming that all the pages of the process are in main memory, the effective memory access time is ______ (ns).
An operating system implements a single level paging. This system uses Translation Lookaside Buffer (TLB) and Physical Address Cache (PAC) as well. TLB has a hit ratio 90...
LRU
867
views
LRU
asked
Nov 3, 2021
Operating System
test-series
operating-system
memory-management
effective-memory-access
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–
1
votes
1
answer
14
Applied Test Series
In a paged memory, the page hit ratio is 0.35. The page fault service time takes 100 ns. The time required to access a page in primary memory is 10 ns. The effective memory access time required to access a page is ____ ns
In a paged memory, the page hit ratio is 0.35. The page fault service time takes 100 ns. The time required to access a page in primary memory is 10 ns. The effective memo...
LRU
691
views
LRU
asked
Oct 20, 2021
Operating System
test-series
operating-system
effective-memory-access
page-fault
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0
votes
1
answer
15
Memory Access Doubt
How many memory accesses are there in this code? LOAD R1, a(RO)
How many memory accesses are there in this code?LOAD R1, a(RO)
aditi19
850
views
aditi19
asked
Apr 1, 2019
CO and Architecture
effective-memory-access
co-and-architecture
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0
votes
1
answer
16
Cache Organization
Can any one help me out with this question : This was asked in MadeEasy CBT held on 23rd jan
Can any one help me out with this question :This was asked in MadeEasy CBT held on 23rd jan
Nandkishor3939
1.0k
views
Nandkishor3939
asked
Jan 25, 2019
CO and Architecture
cache-memory
co-and-architecture
effective-memory-access
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0
votes
2
answers
17
Ace Test Series: Operating System - TLB Effective Access Time
Na462
1.1k
views
Na462
asked
Jan 21, 2019
Operating System
effective-memory-access
operating-system
co-and-architecture
ace-test-series
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0
votes
0
answers
18
Virtual Memory (Self Doubt)
I have a simple doubt, Given a question that says that memory access time is x and page fault service time is y. We apply T = h*x + (1-h)*y Here assuming single level pagetable I suppose x is the time for accessing the page table and getting ... frame I 0) why he considered here an extra access ? Reference : https://gateoverflow.in/85404/gate1990-7-b Help me out here :(
I have a simple doubt, Given a question that says that memory access time is x and page fault service time is y. We applyT = h*x + (1-h)*yHere assuming single level paget...
Na462
266
views
Na462
asked
Jan 17, 2019
Operating System
operating-system
virtual-memory
paging
effective-memory-access
self-doubt
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0
votes
1
answer
19
Effective Access Time
A Computer uses two level Cache L1 and L2 and in 2000 memory references there are 320 misses in L1 and 150 misses in L2. If Miss penalty of L2 is 300 clock cycles, hit time of L1 is 1 clock cycle and hit time in L2 is 10 clock cycle .What is average memory access time ? 3.6 cycles 5.4 cycles 25.06 cycles 4.8 cycles
A Computer uses two level Cache L1 and L2 and in 2000 memory references there are 320 misses in L1 and 150 misses in L2. If Miss penalty of L2 is 300 clock cycles, hit ti...
Na462
870
views
Na462
asked
Jan 12, 2019
CO and Architecture
co-and-architecture
cache-memory
effective-memory-access
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–
0
votes
1
answer
20
Effective memory access time
Suppose: TLB lookup time = 20 ns TLB hit ratio = 80% Memory access time = 75 ns Swap page time = 500,000 ns 50% of pages are dirty OS uses a single level page table What is the effective access time (EAT) if we assume the page fault rate is 10%? Assume the cost toupdate the TLB, the page table, and the frame table (if needed) is negligible.
Suppose: TLB lookup time = 20 nsTLB hit ratio = 80%Memory access time = 75 nsSwap page time = 500,000 ns50% of pages are dirtyOS uses a single level page tableWhat is the...
Hardik Vagadia
1.4k
views
Hardik Vagadia
asked
Jan 3, 2019
Operating System
effective-memory-access
operating-system
page-fault
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–
0
votes
0
answers
21
Effective memory access time
Consider a paging system with a page table stored in memory where memory reference takes 200 nanoseconds and all pages are in memory. What is the effective memory reference time if the hit ratio for the associative registers is 70%, the hitratio for memory ... time, etc takes 100 nanoseconds.). TLB access time is 10ns. The given answer is 299ns but i am getting 290ns.
Consider a paging system with a page table stored in memory where memory reference takes 200 nanoseconds and all pages are in memory. What is the effective memory referen...
Hardik Vagadia
632
views
Hardik Vagadia
asked
Jan 3, 2019
Operating System
effective-memory-access
operating-system
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–
0
votes
1
answer
22
UPPCL 2018AE
Suppose when there is cache “Miss” then memory Access is 30ns and when cache “Hit” then memory access time is 3ns if 80% is cache hit then effective memory access 9ns 8.4ns 3ns 9.10ns
Suppose when there is cache “Miss” then memory Access is 30nsand when cache “Hit” then memory access time is 3nsif 80% is cache hit then effective memory access9n...
pream sagar
1.3k
views
pream sagar
asked
Dec 31, 2018
CO and Architecture
co-and-architecture
cache-memory
effective-memory-access
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–
2
votes
0
answers
23
Self doubt on EMAT
For page fault Some where I see EMAT=page fault (page fault service time) +(1-page fault)(memory access time) BUT somewhere it's like EMAT=page fault (page fault service time + memory access time) +(1-page fault)(memory access time) Which one is correct and why this difference?
For page fault Some where I seeEMAT=page fault (page fault service time) +(1-page fault)(memory access time)BUT somewhere it's likeEMAT=page fault (page fault service tim...
Rishav Kumar Singh
508
views
Rishav Kumar Singh
asked
Dec 26, 2018
Operating System
effective-memory-access
operating-system
page-fault
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–
0
votes
1
answer
24
Co Interrupt
Consider a single-level cache with an access time of 2.5 ns with a block size of 64 bytes. Main memory uses a block transfer capability that has a first word (4 bytes) access time of 50 ns and an access time of 5 ns for each word thereafter. If hit ratio of ... . Answer explain 2.5+0.05(2.5+50+15*5) which is correct? I find made easy accurate with answers for all subjects except Co.
Consider a single-level cache with an access time of 2.5 ns with a block size of 64 bytes. Main memory uses a block transfer capability that has a first word (4 bytes) ac...
Aravind Adithya 1
286
views
Aravind Adithya 1
asked
Dec 24, 2018
CO and Architecture
co-and-architecture
cache-memory
effective-memory-access
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–
0
votes
2
answers
25
Memory Heirarchy Doubt
Consider a single level cache with an access time of 2.5ns with a block size of 64 bytes. Main Memory uses a block transfer capability that has a first word (4 bytes) access time of 50ns and an access time of 5ns for each word ... to consider a Strict memory hierarchy method or Parallel accessing method in Solving these types of questions? By Default which way is followed?
Consider a single level cache with an access time of 2.5ns with a block size of 64 bytes. Main Memory uses a block transfer capability that has a first word (4 bytes) acc...
Ashwani Yadav
926
views
Ashwani Yadav
asked
Dec 22, 2018
CO and Architecture
co-and-architecture
effective-memory-access
cache-memory
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