Recent questions tagged hazards / GATE Overflow for GATE CSE

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1

Morris Mano Edition 3 Exercise 9 Question 23 (Page No. 396)
Draw the logic diagram of the product of sum expression $ Y = (x _1 + x _2’)(x _2 + x _3)$ Show that there is a static 0 hazard when $x _1$ and $x _3$ is equal to zero and $x _2$ goes from 0 to 1.Find a way to remove hazard by adding one more OR gate.

Draw the logic diagram of the product of sum expression$ Y = (x _1 + x _2’)(x _2 + x _3)$Show that there is a static 0 hazard when $x _1$ and $x _3$ is equal to zero a...

ajaysoni1924

731 views

ajaysoni1924 asked Apr 8, 2019

1 votes

0 answers

2

Morris Mano Edition 3 Exercise 9 Question 22 (Page No. 396)
Find a circuit that has no static hazard and implements the boolean function: F(A,B,C,D) = $\sum(0,2,6,7,8,10,12)$

Find a circuit that has no static hazard and implements the boolean function:F(A,B,C,D) = $\sum(0,2,6,7,8,10,12)$

ajaysoni1924

1.3k views

ajaysoni1924 asked Apr 8, 2019

0 votes

1 answer

3

Avoiding pipeline Hazards
Please Confirm.

Please Confirm.

smsubham

461 views

smsubham asked Dec 27, 2018

0 votes

1 answer

4

Data Hazards
Find the data hazards(RAW,WAW,WAR) in the given instructions

Find the data hazards(RAW,WAW,WAR) in the given instructions

Vishnathan

962 views

Vishnathan asked Nov 17, 2018

0 votes

0 answers

5

Data Hazard

Na462

764 views

Na462 asked Nov 14, 2018

2 votes

1 answer

6

Pipeline : Number of RAW dependencies
Consider the below instructions executed on a 5 stage(IF,ID,EX,MA,WB) RISC pipeline with operand forwarding. I1: ADD R0,R1,R2 (R0=R1+R2) I2: SUB R3,R0,R2 I3:MUL R4,R3,R0 I4:DIV R5,R4,R0 How many RAW dependencies?

Consider the below instructions executed on a 5 stage(IF,ID,EX,MA,WB) RISC pipeline with operand forwarding.I1: ADD R0,R1,R2 (R0=R1+R2)I2: SUB R3,R0,R2I3:MUL R4,R3,R0I4:D...

Mk Utkarsh

2.3k views

Mk Utkarsh asked Oct 23, 2018

3 votes

2 answers

7

Pipeline hazards
R1 <- R1+R2 R2 <- R3*R4 R3 <- R4-R1 R2 <- R3+R4 Can someone point out hazards. Thanks :)

R1 <- R1+R2R2 <- R3*R4R3 <- R4-R1R2 <- R3+R4Can someone point out hazards. Thanks :)

gauravkc

1.2k views

gauravkc asked Jan 24, 2018

1 votes

0 answers

8

MOCK TEST

pankaj joshi 1

397 views

pankaj joshi 1 asked Jan 22, 2018

3 votes

0 answers

9

#Data Hazards #Operand Forwarding #CO
Is there any difference in calculating data hazards and dependencies? Doubt 1:I've read that in data dependencies calculation we chose adjacent instructions only? IS THIS TRUE. Doubt 2:Calculation of RAW,WAR,WAW hazards include ... adjacent.IS THIS TRUE There are many sources which are confusing Please Explain how to calculate dependencies and hazards.

Is there any difference in calculating data hazards and dependencies?Doubt 1:I've read that in data dependencies calculation we chose adjacent instructions only? IS THIS ...

rasto mapp

604 views

rasto mapp asked Jan 13, 2018

1 votes

1 answer

10

Various Methods to eliminate Static(0/1) and Dynamic Hazards in Digital Circuits
Hi Guys, What are various techniques to eliminate Static(0/1) and Dynamic Hazards in Digital Circuits ? If you can provide some good reference then it will be really helpful. ping @Puja Mishra, ... , @Anu007, @Hemant Parihar, @ sushmita, @VS @Shweta Nair @Krish__, @Ashwin Kulkarni @reena_kandari and @srestha ji.

Hi Guys,What are various techniques to eliminate Static(0/1) and Dynamic Hazards in Digital Circuits ?If you can provide some good reference then it will be really helpfu...

Chhotu

425 views

Chhotu asked Dec 29, 2017

1 votes

1 answer

11

RAW, WAR, WAW hazards
J1: R1 = 100 J2: R1 = R2 + R4 J3: R2 = R4 + 25 J4: R4 = R1 + R3 J5: R1 = R1 + 30 Give the no of RAW, WAR and WAW hazards

J1: R1 = 100J2: R1 = R2 + R4J3: R2 = R4 + 25J4: R4 = R1 + R3J5: R1 = R1 + 30Give the no of RAW, WAR and WAW hazards

Tuhin Dutta

2.1k views

Tuhin Dutta asked Dec 3, 2017

0 votes

1 answer

12

When to assume Structural hazards exists if not mentioned in instruction pipeline-self doubt
When shall we assume structural hazard?Like if nothing is mentioned if data and instruction are fetched via single port,can we assume 'MA' (memory access stage) and 'IF' (instruction ... it always the case if nothing is told? https://gateoverflow.in/102565/operand-forwarding-in-pipeline

When shall we assume structural hazard?Like if nothing is mentioned if data and instruction are fetched via single port,can we assume 'MA' (memory access stage) and 'IF' ...

Surajit

322 views

Surajit asked Dec 1, 2017

4 votes

0 answers

13

Virtual Gate Test Series: Digital Logic - Static Hazard
In the circuit shown in the figure, the value of input $P$ goes from $0$ to $1$ and that of $Q$ goes from $1$ to $0.$ Which output forms shown the in figure represents the output under a static hazard condition?

In the circuit shown in the figure, the value of input $P$ goes from $0$ to $1$ and that of $Q$ goes from $1$ to $0.$ Which output forms shown the in figure represents th...

Manoja Rajalakshmi A

419 views

Manoja Rajalakshmi A asked Nov 12, 2017

4 votes

1 answer

14

Dependency VS Hazard
Consider following program is executed on a 5 stage RISC pipeline and stages are IF, ID, EX, MA, WB. IF = Instruction Fetch ID = Instruction Decode and fetch register EX = Execution Stage MA = Memory Access WB = Write back register file Program: ... and Hazards.(There is no Structural Dependency) My Answers -> Dependencies = 6, hazards = 3. Someone verify these answer.

Consider following program is executed on a 5 stage RISC pipeline and stages are IF, ID, EX, MA, WB.IF = Instruction FetchID = Instruction Decode and fetch register EX =...

Shubhanshu

2.4k views

Shubhanshu asked Nov 8, 2017

1 votes

0 answers

15

solve structural hazard CPI
A 5-stage pipeline has a Register File that can execute either a Read operation (of 1 or 2 registers) or a Write operation (into only one register), but not both, during every clock cycle. The instruction mix that the processor executes ... has a Register File capable of performing two reads and one write every cycle over the pipeline with the limited Register file?

A 5-stage pipeline has a Register File that can execute either a Read operation (of 1 or 2 registers) or a Write operation (into only one register), but not both, during ...

Howard.xu0527

373 views

Howard.xu0527 asked Sep 29, 2017

2 votes

0 answers

16

RAW hazard
I have gone through several links related to raw harazd.. Some are saying, we consider RAW hazard between adjacent instruction only..EX https://gateoverflow.in/17729/raw-dependencies https://gateoverflow.in/116280/made-easy-co https://gateoverflow.in/21299/war ... https://gateoverflow.in/753/gate2001-12 Iam confuse, in RAW dependency should we look for non adjacent instruction also ??

I have gone through several links related to raw harazd..Some are saying, we consider RAW hazard between adjacent instruction only..EXhttps://gateoverflow.in/17729/raw-de...

stblue

1.4k views

stblue asked Sep 28, 2017

2 votes

3 answers

17

RAW hazard
Find total number of RAW hazards. Doubt: Should I4 - I5 be counted or not ?

Find total number of RAW hazards.Doubt: Should I4 - I5 be counted or not ?

just_bhavana

1.7k views

just_bhavana asked Aug 27, 2017

4 votes

1 answer

18

Test Series (pipelining)
Consider a machine with a 5-stage pipeline with a 1ns clock cycle. The second machine with a 12-stage pipeline with a 0.6ns clock cycle. The 5-stage pipeline experiences a stall due to data hazard for every 5 instructions, whereas 12 stage pipeline experiences 3 stalls ... machine is 5 cycles, what is the speedup of a 12-stage pipeline over 5 stage pipeline--------------?

Consider a machine with a 5-stage pipeline with a 1ns clock cycle. The second machine with a 12-stage pipeline with a 0.6ns clock cycle. The 5-stage pipeline experiences ...

Bishnu Gupta 1

1.5k views

Bishnu Gupta 1 asked Jul 19, 2017

0 votes

1 answer

19

#CSO_pipelining
In flow dependency, instructions level parallelism is possible or not ? How many type of dependency is possible in pipelining ?

In flow dependency, instructions level parallelism is possible or not ?How many type of dependency is possible in pipelining ?

elakashi sharma

287 views

elakashi sharma asked May 15, 2017

0 votes

1 answer

20

structural hazards
Can we completely remove structural hazards..if we have separate intruction memory and data memory?

Can we completely remove structural hazards..if we have separate intruction memory and data memory?

vaishali jhalani

591 views

vaishali jhalani asked Nov 27, 2016

11 votes

4 answers

21

ISRO2016-11
The dynamic hazard problem occurs in combinational circuit alone sequential circuit only Both (a) and (b) None of the above

The dynamic hazard problem occurs incombinational circuit alonesequential circuit onlyBoth (a) and (b)None of the above

Desert_Warrior

11.7k views

Desert_Warrior asked Jul 3, 2016

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