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Recent questions tagged instruction-execution
1
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No of 1 Address 2 Address 0 Address Instructions Practice
I have seen lots of questions like this : A load-store architecture in which memory operation applied only on LOAD and STORE instructions and other all operations are REG-REG instructions. Assume three address architecture. Find the minimum number of ... 3AI: 7 2AI:12 1AI:15 0AI:16 Please comment if anything wrong!!!
I have seen lots of questions like this :A load-store architecture in which memory operation applied only on LOAD and STORE instructions and other all operations are REG-...
squirrel69
232
views
squirrel69
asked
Nov 5, 2023
CO and Architecture
machine-instruction
instruction-format
instruction-execution
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–
3
votes
1
answer
2
Co Arcitecture
A CPU has instructions 12 bits long. The size of an address field is 4 bits. It is possible to have: 14 commands of two addresses 29 commands of an address 48 zero-address instructions. using this command form?
A CPU has instructions 12 bits long. The size of an address field is 4 bits. It is possible to have: 14 commands of two addresses 29 commands of an address 48 zero-addres...
Greepes
237
views
Greepes
asked
Sep 19, 2023
GATE
co-and-architecture
multiple-selects
machine-instruction
instruction-execution
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2
votes
3
answers
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CO and Arcitecture | RISC | Instruction pipelining
MSQ Which among the following statements is/are TRUE for a pipelined RISC computer. PC is usually incremented during Instruction Cycle (IF,ID) PC may be incremented during Execution Cycle (EX,MA,WB) Filling the Accumulator ... during the Instruction Cycle (IF,ID) All non-register memory fetching operations are done in Load instructions only.
MSQWhich among the following statements is/are TRUE for a pipelined RISC computer.PC is usually incremented during Instruction Cycle (IF,ID)PC may be incremented during ...
Souvik33
749
views
Souvik33
asked
Dec 16, 2022
CO and Architecture
pipelining
multiple-selects
co-and-architecture
machine-instruction
instruction-execution
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1
votes
1
answer
4
DRDO CSE 2022 Paper 2 | Question: 3
The execution of a program occurs on a $250 \mathrm{~GHz}$ processor that executes millions of instructions. Type, $\text{CPI}$ (cycles per instruction) and $\%$ of four instructions are provided in the table. \[\begin{array}{|c|c|c|} \ ... end{array}\] Compute the average $\text{CPI}$ and $\text{MIPS}$ (millions of instructions per second) rate of the processor.
The execution of a program occurs on a $250 \mathrm{~GHz}$ processor that executes millions of instructions. Type, $\text{CPI}$ (cycles per instruction) and $\%$ of four ...
admin
460
views
admin
asked
Dec 15, 2022
CO and Architecture
drdocse-2022-paper2
co-and-architecture
instruction-execution
5-marks
descriptive
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–
0
votes
1
answer
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Made Esy Test Series 2022 | COA | Subject wise Q.no 17
** MSQ ** Consider the following sequence of micro-operations (μO) on a system used for instruction fetch: Where MAR is memory address register, PC is program counter, MBR is memory buffer register and IR is instruction register. And ... the following μO's can execute parallely without conflict. μO2 and μO3 μO1 and μO3 μO4 and μO3 μO2 and μO4
MSQ Consider the following sequence of micro-operations (μO) on a system used for instruction fetch:Where MAR is memory address register, PC is program counter, MBR i...
Souvik33
529
views
Souvik33
asked
Nov 23, 2022
CO and Architecture
co-and-architecture
made-easy-test-series
multiple-selects
test-series
instruction-execution
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–
0
votes
1
answer
6
#Exam
Pipe line consists of 5 stages , add instruction takes 2 cycles in EX stage, mul instruction takes 3 cycles in EX stage .. If we don't use buffer in between stages(no store and forward) , what is the time taken to execute two instruction add,mul???
Pipe line consists of 5 stages , add instruction takes 2 cycles in EX stage, mul instruction takes 3 cycles in EX stage .. If we don't use buffer in between stages(no sto...
RamaSivaSubrahmanyam
413
views
RamaSivaSubrahmanyam
asked
Sep 14, 2022
CO and Architecture
co-and-architecture
pipelining
instruction-execution
numerical-answers
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–
1
votes
1
answer
7
Nptel Assignment Question
The instruction $LDA$ $FF0$ (machine code of $LDA$ is $5$) is stored in location $7F0$. The contents in memory location $FF0$ are loaded into accumulator. After its execution, accumulator stores value $8$. The figure below shows a snapshot of the registers and their contents. ... $MAR = 7F0$, $IR = 5FF0$, $MBR = 5FF0$ $MAR = FF1$, $IR = 5FF0$, $MBR = 7F0$
The instruction $LDA$ $FF0$ (machine code of $LDA$ is $5$) is stored in location $7F0$. The contents in memory location $FF0$ are loaded into accumulator. After its exe...
Yaman Sahu
523
views
Yaman Sahu
asked
Oct 7, 2021
CO and Architecture
co-and-architecture
nptel-quiz
instruction-execution
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–
23
votes
4
answers
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GATE CSE 2021 Set 2 | Question: 53
Consider a pipelined processor with $5$ stages, $\text{Instruction Fetch} (\textsf{IF})$, $\text{Instruction Decode} \textsf{(ID)}$, $\text{Execute } \textsf{(EX)}$, $\text{Memory Access } \textsf{(MEM)}$ ... $\textit{Speedup} $ achieved in executing the given instruction sequence on the pipelined processor (rounded to $2$ decimal places) is _____________
Consider a pipelined processor with $5$ stages, $\text{Instruction Fetch} (\textsf{IF})$, $\text{Instruction Decode} \textsf{(ID)}$, $\text{Execute } \textsf{(EX)}$, $\te...
Arjun
15.1k
views
Arjun
asked
Feb 18, 2021
CO and Architecture
gatecse-2021-set2
co-and-architecture
pipelining
instruction-execution
numerical-answers
2-marks
+
–
2
votes
3
answers
9
Ace Test Series: CO & Architecture - Instruction Execution
CPU can leave current instruction execution, without completing it for : Service of interrupt DMA Both Neither
CPU can leave current instruction execution, without completing it for :Service of interruptDMABothNeither
Na462
670
views
Na462
asked
Jan 21, 2019
CO and Architecture
co-and-architecture
dma
ace-test-series
instruction-execution
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0
votes
0
answers
10
MadeEasy Full Length Test 2018: CO & Architecture - Instruction Execution
A particular parallel program computation requires 100 seconds when executed on a single processor. If 40 percent of this computation is “ inherently sequential ”, then what are the theoretically best elapsed times for this program running with 2 and 4 processors, respectively ?
A particular parallel program computation requires 100 seconds when executed on a single processor. If 40 percent of this computation is “ inherently sequential ”, th...
mehul vaidya
621
views
mehul vaidya
asked
Jan 12, 2019
CO and Architecture
co-and-architecture
instruction-execution
made-easy-test-series
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–
1
votes
1
answer
11
Calculate number of times Zero Flag is Reset
I am getting 37.
I am getting 37.
Shubhanshu
1.2k
views
Shubhanshu
asked
Jan 8, 2019
CO and Architecture
co-and-architecture
instruction-execution
machine-instruction
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–
0
votes
1
answer
12
Zeal Test Series 2018: CO & Architecture - Instruction Excecution
Prince Sindhiya
1.1k
views
Prince Sindhiya
asked
Dec 8, 2018
CO and Architecture
zeal
co-and-architecture
instruction-execution
zeal2018
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–
1
votes
0
answers
13
Gradeup mocktest
In a pipelined RISC computer, where arithmetic instructions and Load/store instructions are carried out, which of the following method will not definitely help in faster execution when only load/store instruction are performed? a. increasing clock speed b. ... in the program then again forwarding that to the load instruction will increase the speed of the computation. Please guide.
In a pipelined RISC computer, where arithmetic instructions and Load/store instructions are carried out, which of the following method will not definitely help in faster ...
V MIDHUN 2
265
views
V MIDHUN 2
asked
Mar 23, 2018
CO and Architecture
test-series
instruction-execution
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–
1
votes
1
answer
14
MadeEasy Test Series: CO & Architecture - Instruction Execution
answer given is 3,2 the address which will be present in branch instruction will be indirect address or not?
answer given is 3,2the address which will be present in branch instruction will be indirect address or not?
charul
288
views
charul
asked
Jan 7, 2018
CO and Architecture
made-easy-test-series
co-and-architecture
instruction-execution
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–
54
votes
4
answers
15
GATE CSE 2017 Set 1 | Question: 49
Consider a RISC machine where each instruction is exactly $4$ bytes long. Conditional and unconditional branch instructions use PC-relative addressing mode with Offset specified in bytes to the target location of the branch instruction. Further the Offset is ... $i,$ then the decimal value of the Offset is ____________ .
Consider a RISC machine where each instruction is exactly $4$ bytes long. Conditional and unconditional branch instructions use PC-relative addressing mode with Offset sp...
Arjun
14.4k
views
Arjun
asked
Feb 14, 2017
CO and Architecture
gatecse-2017-set1
co-and-architecture
normal
numerical-answers
instruction-execution
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0
votes
1
answer
16
MadeEasy Subject Test: CO & Architecture - Instruction Execution
vaishali jhalani
394
views
vaishali jhalani
asked
Feb 4, 2017
CO and Architecture
co-and-architecture
made-easy-test-series
instruction-execution
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–
0
votes
1
answer
17
MadeEasy Subject Test: CO & Architecture - Instruction Execution
Is this the correct answer? Explain. (as word size is 32 bits)
Is this the correct answer? Explain. (as word size is 32 bits)
naveen81
281
views
naveen81
asked
Feb 1, 2017
CO and Architecture
made-easy-test-series
co-and-architecture
instruction-execution
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–
9
votes
3
answers
18
GATE CSE 1990 | Question: 4-iii
State whether the following statements are TRUE or FALSE with reason: The flags are affected when conditional CALL or JUMP instructions are executed.
State whether the following statements are TRUE or FALSE with reason:The flags are affected when conditional CALL or JUMP instructions are executed.
makhdoom ghaya
3.2k
views
makhdoom ghaya
asked
Nov 23, 2016
CO and Architecture
gate1990
true-false
co-and-architecture
instruction-execution
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–
0
votes
0
answers
19
MadeEasy Test Series: CO & Architecture - Instruction Execution
vikas khuswaha
521
views
vikas khuswaha
asked
Feb 2, 2016
CO and Architecture
made-easy-test-series
co-and-architecture
instruction-execution
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–
0
votes
1
answer
20
MadeEasy Test Series: CO & Architecture - Instruction Execution
Each word is 4b and there are 10 words 40 B 3000+40B +1 What is the actual solution ?
Each word is 4b and there are 10 words40 B3000+40B +1What is the actual solution ?
pC
835
views
pC
asked
Jan 30, 2016
CO and Architecture
made-easy-test-series
co-and-architecture
instruction-execution
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–
1
votes
0
answers
21
Ace Test Series: CO & Architecture - Instruction Execution
As far as I know, HALT is always implemented as... HALT = Here: JMP Here Until user close the application, it keeps looping itself. So the address on the stack should be 1024 and not 1028.
As far as I know, HALT is always implemented as...HALT = Here: JMP HereUntil user close the application, it keeps looping itself. So the address on the stack should be 10...
Tushar Shinde
454
views
Tushar Shinde
asked
Jan 24, 2016
CO and Architecture
ace-test-series
co-and-architecture
instruction-execution
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–
16
votes
2
answers
22
GATE CSE 1995 | Question: 1.2
Which of the following statements is true? ROM is a Read/Write memory PC points to the last instruction that was executed Stack works on the principle of LIFO All instructions affect the flags
Which of the following statements is true?ROM is a Read/Write memoryPC points to the last instruction that was executedStack works on the principle of LIFOAll instruction...
Kathleen
4.7k
views
Kathleen
asked
Oct 8, 2014
CO and Architecture
gate1995
co-and-architecture
normal
instruction-execution
+
–
44
votes
5
answers
23
GATE CSE 2006 | Question: 43
Consider a new instruction named branch-on-bit-set (mnemonic bbs). The instruction bbs reg, pos, label jumps to label if bit in position pos of register operand reg is one. A register is $32$ -bits wide and the bits are numbered $0$ to $31,$ bit ... $ mask\leftarrow \text{0xffffffff} << pos$ $ mask\leftarrow pos $ $ mask\leftarrow \text{0xf}$
Consider a new instruction named branch-on-bit-set (mnemonic bbs). The instruction “bbs reg, pos, label” jumps to label if bit in position pos of register operand reg...
Rucha Shelke
10.9k
views
Rucha Shelke
asked
Sep 26, 2014
CO and Architecture
gatecse-2006
co-and-architecture
normal
instruction-execution
+
–
16
votes
2
answers
24
GATE CSE 2002 | Question: 1.13
Which of the following is not a form of memory instruction cache instruction register instruction opcode translation look-a-side buffer
Which of the following is not a form of memoryinstruction cacheinstruction registerinstruction opcodetranslation look-a-side buffer
Kathleen
6.1k
views
Kathleen
asked
Sep 15, 2014
CO and Architecture
gatecse-2002
co-and-architecture
easy
instruction-execution
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–
7
votes
4
answers
25
GATE CSE 1992 | Question: 01-iv
Many of the advanced microprocessors prefetch instructions and store it in an instruction buffer to speed up processing. This speed up is achieved because ________
Many of the advanced microprocessors prefetch instructions and store it in an instruction buffer to speed up processing. This speed up is achieved because ________
Kathleen
3.0k
views
Kathleen
asked
Sep 12, 2014
CO and Architecture
gate1992
co-and-architecture
easy
instruction-execution
fill-in-the-blanks
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–
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