Recent questions tagged isro2009 / GATE Overflow for GATE CSE

56 votes

3 answers

61

GATE IT 2006 | Question: 39, ISRO2009-42
Which of the following statements about relative addressing mode is FALSE? It enables reduced instruction size It allows indexing of array element with same instruction It enables easy relocation of data It enables faster address calculation than absolute addressing

Which of the following statements about relative addressing mode is FALSE?It enables reduced instruction sizeIt allows indexing of array element with same instructionIt e...

Ishrat Jahan

14.9k views

Ishrat Jahan asked Oct 31, 2014

24 votes

3 answers

62

GATE IT 2006 | Question: 7, ISRO2009-41
The addition of $4-bit$, two's complement, binary numbers $1101$ and $0100$ results in $0001$ and an overflow $1001$ and no overflow $0001$ and no overflow $1001$ and an overflow

The addition of $4-bit$, two's complement, binary numbers $1101$ and $0100$ results in$0001$ and an overflow$1001$ and no overflow$0001$ and no overflow$1001$ and an over...

Ishrat Jahan

14.5k views

Ishrat Jahan asked Oct 31, 2014

15 votes

2 answers

63

GATE CSE 2006 | Question: 56, ISRO2009-58
Consider the following code written in a pass-by-reference language like FORTRAN and these statements about the code. subroutine swap(ix,iy) it = ix L1 : ix = iy L2 : iy = it end ia = 3 ib = 8 call swap (ia, ib+5) print *, ia, ib end ... : The program will print 13 and -2 Exactly the following set of statement(s) is correct: S1 and S2 S1 and S4 S3 S1 and S5

Consider the following code written in a pass-by-reference language like FORTRAN and these statements about the code. subroutine swap(ix,iy) it = ix L1 : ix = iy L2 : iy ...

Rucha Shelke

6.8k views

Rucha Shelke asked Sep 26, 2014

24 votes

5 answers

64

GATE CSE 2005 | Question: 16, ISRO2009-18, ISRO2015-2
The range of integers that can be represented by an $n$ bit $2’s$ complement number system is: $-2^{n-1} \text{ to } (2^{n-1} -1)$ $-(2^{n-1} -1) \text{ to } (2^{n-1} -1)$ $-2^{n-1} \text{ to } 2^{n-1}$ $-(2^{n-1} +1) \text{ to } (2^{n-1} -1)$

The range of integers that can be represented by an $n$ bit $2’s$ complement number system is:$-2^{n-1} \text{ to } (2^{n-1} -1)$$-(2^{n-1} -1) \text{ to } (2^{n-1} -1)...

Kathleen

9.7k views

Kathleen asked Sep 22, 2014

32 votes

4 answers

65

GATE CSE 2007 | Question: 37, ISRO2009-37
Consider a pipelined processor with the following four stages: IF: Instruction Fetch ID: Instruction Decode and Operand Fetch EX: Execute WB: Write Back The IF, ID and WB stages take one clock cycle each to complete the operation. The number of clock cycles for the EX ... $ R5$-$R4} \\ \end{array}$ $7$ $8$ $10$ $14$

Consider a pipelined processor with the following four stages:IF: Instruction FetchID: Instruction Decode and Operand FetchEX: ExecuteWB: Write BackThe IF, ID and WB stag...

Kathleen

16.0k views

Kathleen asked Sep 21, 2014

24 votes

3 answers

66

GATE CSE 2005 | Question: 12, ISRO2009-64
Let $f(x)$ be the continuous probability density function of a random variable $x$, the probability that $a < x \leq b$, is : $f(b-a)$ $f(b) - f(a)$ $\int\limits_a^b f(x) dx$ $\int\limits_a^b xf (x)dx$

Let $f(x)$ be the continuous probability density function of a random variable $x$, the probability that $a < x \leq b$, is :$f(b-a)$$f(b) - f(a)$$\int\limits_a^b f(x) dx...

gatecse

11.6k views

gatecse asked Sep 21, 2014

32 votes

5 answers

67

GATE CSE 2004 | Question: 38, ISRO2009-27
Assume that the operators $+, -, \times$ are left associative and $^\hat{}$ is right associative. The order of precedence (from highest to lowest) is $ \ ^\hat{}, \times, +, -$ ... $-+a\times bc \ \ \hat{} \ \ \ \hat{} \ \ def$

Assume that the operators $+, -, \times$ are left associative and $^\hat{}$ is right associative. The order of precedence (from highest to lowest) is $ \ ^\hat{}, \times,...

Kathleen

12.9k views

Kathleen asked Sep 18, 2014

27 votes

6 answers

68

GATE CSE 2004 | Question: 4, ISRO2009-26
The following numbers are inserted into an empty binary search tree in the given order: $10, 1, 3, 5, 15, 12, 16$. What is the height of the binary search tree (the height is the maximum distance of a leaf node from the root)? $2$ $3$ $4$ $6$

The following numbers are inserted into an empty binary search tree in the given order: $10, 1, 3, 5, 15, 12, 16$. What is the height of the binary search tree (the heigh...

Kathleen

22.6k views

Kathleen asked Sep 18, 2014

56 votes

6 answers

69

GATE CSE 2003 | Question: 82, ISRO2009-1
The subnet mask for a particular network is $255.255.31.0.$ Which of the following pairs of $\text{IP}$ addresses could belong to this network? $172.57.88.62$ and $172.56.87.23$ $10.35.28.2$ and $10.35.29.4$ $191.203.31.87$ and $191.234.31.88$ $128.8.129.43$ and $128.8.161.55$

The subnet mask for a particular network is $255.255.31.0.$ Which of the following pairs of $\text{IP}$ addresses could belong to this network?$172.57.88.62$ and $172.56....

Kathleen

29.2k views

Kathleen asked Sep 17, 2014

65 votes

4 answers

70

GATE CSE 2003 | Question: 63, ISRO2009-25
A data structure is required for storing a set of integers such that each of the following operations can be done in $O(\log n)$ time, where $n$ is the number of elements in the set. Deletion of the smallest element Insertion of an ... used but not a heap Both balanced binary search tree and heap can be used Neither balanced search tree nor heap can be used

A data structure is required for storing a set of integers such that each of the following operations can be done in $O(\log n)$ time, where $n$ is the number of elements...

Kathleen

20.3k views

Kathleen asked Sep 17, 2014

51 votes

5 answers

71

GATE CSE 2003 | Question: 29, ISRO2009-73
Which of the following scenarios may lead to an irrecoverable error in a database system? A transaction writes a data item after it is read by an uncommitted transaction A transaction reads a data item after it is read by an ... it is written by a committed transaction A transaction reads a data item after it is written by an uncommitted transaction

Which of the following scenarios may lead to an irrecoverable error in a database system?A transaction writes a data item after it is read by an uncommitted transactionA ...

Kathleen

14.8k views

Kathleen asked Sep 16, 2014

44 votes

5 answers

72

GATE CSE 2003 | Question: 25, ISRO2009-12
Using a larger block size in a fixed block size file system leads to better disk throughput but poorer disk space utilization better disk throughput and better disk space utilization poorer disk throughput but better disk space utilization poorer disk throughput and poorer disk space utilization

Using a larger block size in a fixed block size file system leads tobetter disk throughput but poorer disk space utilizationbetter disk throughput and better disk space u...

Kathleen

15.0k views

Kathleen asked Sep 16, 2014

25 votes

3 answers

73

GATE CSE 2003 | Question: 19, ISRO2009-24
Suppose the numbers $7, 5, 1, 8, 3, 6, 0, 9, 4, 2$ ... $9 \ 8 \ 6 \ 4 \ 2 \ 3 \ 0 \ 1 \ 5 \ 7$

Suppose the numbers $7, 5, 1, 8, 3, 6, 0, 9, 4, 2$ are inserted in that order into an initially empty binary search tree. The binary search tree uses the usual ordering o...

Kathleen

23.5k views

Kathleen asked Sep 16, 2014

65 votes

5 answers

74

GATE CSE 2003 | Question: 8, ISRO2009-53
Let $\text{G}$ be an arbitrary graph with $n$ nodes and $k$ components. If a vertex is removed from $\text{G}$, the number of components in the resultant graph must necessarily lie down between $k$ and $n$ $k-1$ and $k+1$ $k-1$ and $n-1$ $k+1$ and $n-k$

Let $\text{G}$ be an arbitrary graph with $n$ nodes and $k$ components. If a vertex is removed from $\text{G}$, the number of components in the resultant graph must neces...

Kathleen

15.4k views

Kathleen asked Sep 16, 2014

41 votes

11 answers

75

GATE CSE 2006 | Question: 09, ISRO2009-35
A CPU has $24$-$bit$ instructions. A program starts at address $300$ (in decimal). Which one of the following is a legal program counter (all values in decimal)? $400$ $500$ $600$ $700$

A CPU has $24$-$bit$ instructions. A program starts at address $300$ (in decimal). Which one of the following is a legal program counter (all values in decimal)?$400$$500...

Rucha Shelke

16.1k views

Rucha Shelke asked Sep 16, 2014

39 votes

4 answers

76

GATE CSE 2006 | Question: 06, ISRO2009-14
Consider three CPU-intensive processes, which require $10$, $20$ and $30$ time units and arrive at times $0$, $2$ and $6$, respectively. How many context switches are needed if the operating system implements a shortest remaining time first scheduling algorithm? Do not count the context switches at time zero and at the end. $1$ $2$ $3$ $4$

Consider three CPU-intensive processes, which require $10$, $20$ and $30$ time units and arrive at times $0$, $2$ and $6$, respectively. How many context switches are nee...

Rucha Shelke

15.9k views

Rucha Shelke asked Sep 16, 2014

30 votes

3 answers

77

GATE CSE 2006 | Question: 1, ISRO2009-57
Consider the polynomial $p(x) = a_0 + a_1x + a_2x^2 + a_3x^3$ , where $a_i \neq 0$, $\forall i$. The minimum number of multiplications needed to evaluate $p$ on an input $x$ is: 3 4 6 9

Consider the polynomial $p(x) = a_0 + a_1x + a_2x^2 + a_3x^3$ , where $a_i \neq 0$, $\forall i$. The minimum number of multiplications needed to evaluate $p$ on an input ...

gatecse

11.4k views

gatecse asked Sep 15, 2014

41 votes

6 answers

78

GATE CSE 2008 | Question: 64, ISRO2009-13
Which of the following statements about synchronous and asynchronous I/O is NOT true? An ISR is invoked on completion of I/O in synchronous I/O but not in asynchronous I/O In both synchronous and asynchronous I/O, an ISR (Interrupt Service ... process waiting for the completion of I/O is woken up by the ISR that is invoked after the completion of I/O

Which of the following statements about synchronous and asynchronous I/O is NOT true?An ISR is invoked on completion of I/O in synchronous I/O but not in asynchronous I/O...

Kathleen

17.7k views

Kathleen asked Sep 12, 2014

39 votes

3 answers

79

GATE CSE 2008 | Question: 37, ISRO2009-38
The use of multiple register windows with overlap causes a reduction in the number of memory accesses for: Function locals and parameters Register saves and restores Instruction fetches $\text{I}$ only $\text{II}$ only $\text{III}$ only $\text{I}, \text{II}$ and $\text{III}$

The use of multiple register windows with overlap causes a reduction in the number of memory accesses for:Function locals and parametersRegister saves and restoresInstruc...

Kathleen

19.4k views

Kathleen asked Sep 12, 2014

58 votes

4 answers

80

GATE CSE 2008 | Question: 33, ISRO2009-80
Which of the following is/are true of the auto-increment addressing mode? It is useful in creating self-relocating code If it is included in an Instruction Set Architecture, then an additional ALU is required for effective address calculation The amount of increment depends on the size of the data item accessed I only II only III only II and III only

Which of the following is/are true of the auto-increment addressing mode?It is useful in creating self-relocating codeIf it is included in an Instruction Set Architecture...

Kathleen

18.5k views

Kathleen asked Sep 12, 2014

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