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Recent questions tagged memory-interfacing

1 votes
0 answers
32
Design and simulate a 1m*16 memory module using 512k*8 SRAM and perform read and write operation
I have a projecp to submit please help me to design and simulate a 1m * 16 memory module using 512k * 8 SRAM and perform read and write operations for the above memory
I have a projecp to submit please help me to design and simulate a 1m * 16 memory module using 512k * 8 SRAM and perform read and write operations for the above memory
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0 votes
1 answer
34
ROM system
How many address and data lines in 1M×16 ROM system
How many address and data lines in 1M×16 ROM system
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0 votes
1 answer
35
Assignment
How many 512×8 RAM chips are needed to provide a memory capacity of 2048 bytes
How many 512×8 RAM chips are needed to provide a memory capacity of 2048 bytes
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2 votes
1 answer
37
Memory interfacing
A memory constructed with 2B words and capacity of memory $2^{18}$ bits. Number of decoder required and type of decoder if memory built using $1K\times 4$ RAM chips? (if possible give some reference and diagram)
A memory constructed with 2B words and capacity of memory $2^{18}$ bits. Number of decoder required and type of decoder if memory built using $1K\times 4$ RAM chips?(if p...
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2 votes
1 answer
39
Computer organisation
I know that correct answer is none of these But I need explanation with answer
I know that correct answer is none of these But I need explanation with answer
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1 votes
1 answer
44
16bit vs 32bit vs 64bit Memory interfacing
In 16 bit processor like 8086, we have the concept of big Endian and small Endian which is related to even and odd bank of memory used in memory address interpretation. For 32 bit and 64 bit, such mechanism exist or not?
In 16 bit processor like 8086, we have the concept of big Endian and small Endian which is related to even and odd bank of memory used in memory address interpretation.Fo...
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12 votes
2 answers
47
ISRO2017-18
How many $128\times 8$ bit RAMs are required to design $32\;\text{K}\times 32$ bit RAM? $512$ $1024$ $128$ $32$
How many $128\times 8$ bit RAMs are required to design $32\;\text{K}\times 32$ bit RAM?$512$$1024$$128$$32$
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1 votes
0 answers
48
ISRO2013-ECE Computer architecture
A memory system of size $16 \;\text{K}$ bytes is required to be designed using memory chips which have $12$ address lines and $4$ data lines each. The number of such chips required to design the system is: $2$ $4$ $8$ $16$
A memory system of size $16 \;\text{K}$ bytes is required to be designed using memory chips which have $12$ address lines and $4$ data lines each. The number of such chip...
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0 votes
3 answers
50
Cache memory
Is it compulsory that the block sizes of the main memory and the cache memory are always equal?
Is it compulsory that the block sizes of the main memory and the cache memory are always equal?
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4 votes
0 answers
55
GATE CSE 1990 | Question: 4-iv
State whether the following statements are TRUE or FALSE with reason: Transferring data in blocks from the main memory to the cache memory enables an interleaved main memory unit to operate at its maximum speed.
State whether the following statements are TRUE or FALSE with reason:Transferring data in blocks from the main memory to the cache memory enables an interleaved main memo...
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0 votes
0 answers
57
computer organization (co)
Why different clock cycle is needed for sending address and control signal . why not in one cycle?
Why different clock cycle is needed for sending address and control signal . why not in one cycle?
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