Recent questions tagged memory-management / GATE Overflow for GATE CSE

1 votes

1 answer

61

Gate@Zeal 2023
Ans: 3KB

Ans: 3KB

SKMAKM

532 views

SKMAKM asked Oct 2, 2022

2 votes

0 answers

62

Operating System: Self Doubt - Memory Management
Considering a system with Single-Level page table, with a TLB to reduce the access time of pages. A cache is also provided with the main memory. All the pages ultimately reside in MM. (assuming there's no page fault). Let, TLB Hit Ratio = x TLB Access ... for TLB miss it will be (a+c+p). But if this is true, why can't we store Page Table in a Cache?

Considering a system with Single-Level page table, with a TLB to reduce the access time of pages. A cache is also provided with the main memory. All the pages ultimately ...

DebRC

366 views

DebRC asked Sep 14, 2022

0 votes

0 answers

63

Computer Organization and Architecture
Please clarify the fourth option only. My doubt: if the same word in requires repeatedly, then for the first the word will be miss and there after it is continuously in use how it can be miss.

Please clarify the fourth option only.My doubt: if the same word in requires repeatedly, then for the first the word will be miss and there after it is continuously in u...

Overflow04

286 views

Overflow04 asked Sep 3, 2022

0 votes

0 answers

64

Computer Organization and Architecture
While calculating the average read time , why 0.9*10 + 0.1*(10+110) is not used. .i.e. why cache time is not added in miss frequency.

While calculating the average read time , why 0.9*10 + 0.1*(10+110) is not used. .i.e. why cache time is not added in miss frequency.

Overflow04

297 views

Overflow04 asked Sep 3, 2022

0 votes

1 answer

65

Which consumes less memory: opening many tabs on the same browser window or opening few tabs on many browser windows?

Nisha Bharti

312 views

Nisha Bharti asked Sep 2, 2022

0 votes

0 answers

66

Operating System
How to solve this question.

How to solve this question.

Overflow04

331 views

Overflow04 asked Sep 1, 2022

0 votes

0 answers

67

Best Open Video Playlist for Memory Management Topic | Operating Systems
Please list out the best free available video playlist for Memory Management from Operating Systems as an answer here (only one playlist per answer). We'll then select the best playlist and add to GO classroom video ... ones are more likely to be selected as best. For the full list of selected videos please see here

Please list out the best free available video playlist for Memory Management from Operating Systems as an answer here (only one playlist per answer). We'll then select th...

makhdoom ghaya

187 views

makhdoom ghaya asked Aug 20, 2022

0 votes

0 answers

68

What is the empty 4 bytes below the "valid" variable?
int main(int argc, char *argv[]) { int valid = 0; char str1[8] = "start"; char str2[8]; gets(str2); if (strncmp(str1, str2, 8) == 0) valid = 1; printf("buffer1: str1(%s), str2(%s), valid(%d)\n", str1, str2, valid); }

int main(int argc, char *argv[]) { int valid = 0; char str1[8] = "start"; char str2[8]; gets(str2); if (strncmp(str1, str2, 8) == 0) valid = 1; printf("buffer1: str1(%s),...

Tejeshwara

469 views

Tejeshwara asked Jun 12, 2022

23 votes

2 answers

69

GATE CSE 2022 | Question: 28
Which one of the following statements is $\text{FALSE}?$ The $\text{TLB}$ performs an associative search in parallel on all its valid entries using page number of incoming virtual address. If the virtual address of a word given by $\text{CPU}$ has a ... $\text{V2}$ map to the same value while hashing, then the memory access time of these addresses will not be the same.

Which one of the following statements is $\text{FALSE}?$The $\text{TLB}$ performs an associative search in parallel on all its valid entries using page number of incoming...

Arjun

8.1k views

Arjun asked Feb 15, 2022

1 votes

1 answer

70

GATE Overflow Test Series | Mock GATE | Test 6 | Question: 58
Consider a CPU using $32$ bit address space. The size of the physical memory in use is $256$ MB and the page size is $4\:\text{Kilo bytes}.$ If the size of a Page Table Entry is four bytes for standard page table and eight bytes for inverted page ... $2^{22}\;\text{bytes},\;2^{19}\;\text{bytes}$

Consider a CPU using $32$ bit address space. The size of the physical memory in use is $256$ MB and the page size is $4\:\text{Kilo bytes}.$ If the size of a Page Table E...

Arjun

111 views

Arjun asked Jan 30, 2022

0 votes

1 answer

71

Gate Applied Test Series
Question: Consider a system using a segmented paging architecture. The segment is divided into 8k pages each of size 2k words . The segment table is divided into 256 k pages each of size 512 words. The page table entry size requires 64 bits . The frame number requires 22 bits ... address (LA). Note: 1 Word = 1 Byte Options Are: A. 51 bits B. 61 bits C. 33 bits D. 64 bits

Question: Consider a system using a segmented paging architecture. The segment is divided into 8k pages each of size 2k words . The segment table is divided into 256 k p...

lalitver10

1.3k views

lalitver10 asked Jan 11, 2022

1 votes

1 answer

72

Memory Management
In a virtual memory system, size of the virtual address is 32-bit, size of the physical address is 30-bit, page size is 4 KByte and size of each page table entry is 32-bit. The main memory is word addressable and word size is 4Bytes. Find the maximum number of bits that can be used for storing other information ?

In a virtual memory system, size of the virtual address is 32-bit, size of the physical address is 30-bit, page size is 4 KByte and size of each page table entry is 32-bi...

Vidya Sagar

1.2k views

Vidya Sagar asked Jan 3, 2022

2 votes

2 answers

73

Gate Applied course Test series
What is answer for this question and also please explain the approach

What is answer for this question and also please explain the approach

Dheeraj Varma

1.2k views

Dheeraj Varma asked Nov 16, 2021

0 votes

1 answer

74

Applied Test Series
An operating system implements a single level paging. This system uses Translation Lookaside Buffer (TLB) and Physical Address Cache (PAC) as well. TLB has a hit ratio 90%. PAC has a miss ratio of 20%. Main memory access time, TLB access time and ... ns respectively. Assuming that all the pages of the process are in main memory, the effective memory access time is ______ (ns).

An operating system implements a single level paging. This system uses Translation Lookaside Buffer (TLB) and Physical Address Cache (PAC) as well. TLB has a hit ratio 90...

LRU

866 views

LRU asked Nov 3, 2021

1 votes

0 answers

75

Page Table Entries in page Table
In Page Table,page-frame address entries are static or Dynamic means whether they are changed or not??(Consider 1-level page table)

In Page Table,page-frame address entries are static or Dynamic means whether they are changed or not??(Consider 1-level page table)

lalitver10

572 views

lalitver10 asked Oct 21, 2021

1 votes

1 answer

76

Applied Practice test
Suppose: TLB lookup time = 20 ns TLB hit ratio = 80% Memory access time = 75 ns PFST = 500,000 ns 50% of the pages are dirty OS uses a single level page table What is the approximated effective access time (EAT) if we assume the page fault rate is 10%? Assume the cost to update the TLB, the page table, and the frame table (if needed) is negligible.

Suppose: TLB lookup time = 20 nsTLB hit ratio = 80%Memory access time = 75 nsPFST = 500,000 ns50% of the pages are dirtyOS uses a single level page tableWhat is the appro...

darshak_devani

834 views

darshak_devani asked Oct 18, 2021

2 votes

0 answers

77

Applied Test Series
A hypothetical system OSXZ_09 implements paging. Given LAS = 4 GB, PAS = 64 MB, Page size = 4 KB. A protection bit and a reference bit is also present in a page table entry. Then the size of the innermost page table is ____ B. Note : The memory is byte addressable.

A hypothetical system OSXZ_09 implements paging. Given LAS = 4 GB, PAS = 64 MB, Page size = 4 KB. A protection bit and a reference bit is also present in a page table ent...

LRU

902 views

LRU asked Oct 11, 2021

61 votes

4 answers

78

GATE CSE 2021 Set 2 | Question: 48
Consider a three-level page table to translate a $39-$bit virtual address to a physical address as shown below: The page size is $\text{4 KB} \;(1\text{KB}=2^{10}$ bytes$)$ and page table entry size at every level is $8$ bytes. A ... $P$ across all levels is _________ $\text{KB}$.

Consider a three-level page table to translate a $39-$bit virtual address to a physical address as shown below:The page size is $\text{4 KB} \;(1\text{KB}=2^{10}$ bytes$)...

Arjun

28.6k views

Arjun asked Feb 18, 2021

4 votes

1 answer

79

GATE Overflow Test Series | Mock GATE | Test 3 | Question: 15
An operating system has $42$ bits logical address. On a certain embedded device physical address space is only $16$ bits. If page size is $4$ KB and page table entries are of $32$ bits, the size of the inverted page table (in bytes) will be _______

An operating system has $42$ bits logical address. On a certain embedded device physical address space is only $16$ bits. If page size is $4$ KB and page table entries ar...

gatecse

315 views

gatecse asked Jan 26, 2021

16 votes

2 answers

80

GATE Overflow Test Series | Mock GATE | Test 2 | Question: 19
Suppose the time to service a page fault is on the average $100$ microseconds, while a memory access on average takes $20$ nanoseconds. What should be the maximum number of page faults per million-page accesses in order to guarantee a page fault overhead of less than $10\%?$

Suppose the time to service a page fault is on the average $100$ microseconds, while a memory access on average takes $20$ nanoseconds. What should be the maximum number ...

gatecse

1.1k views

gatecse asked Jan 17, 2021

8 votes

1 answer

81

GATE Overflow Test Series | Mock GATE | Test 2 | Question: 37
Let a memory have four free blocks of sizes $\text{4k, 8k, 20k, 2k}$. These blocks are allocated following the first-fit strategy. The allocation requests are stored in a queue as shown below from multiple processes executing ... $T_6$ will be completed will be ________

Let a memory have four free blocks of sizes $\text{4k, 8k, 20k, 2k}$. These blocks are allocated following the first-fit strategy. The allocation requests are stored in a...

gatecse

471 views

gatecse asked Jan 17, 2021

5 votes

1 answer

82

GATE Overflow Test Series | Mock GATE | Test 2 | Question: 38
Consider a computer system with $32$-bit virtual addressing and page size of sixteen kilobytes. If the computer system has a one-level page table per process and each page table entry requires $40$ bits, then the size of the per-process page table is ________ megabytes.

Consider a computer system with $32$-bit virtual addressing and page size of sixteen kilobytes. If the computer system has a one-level page table per process and each pag...

gatecse

372 views

gatecse asked Jan 17, 2021

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