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Pipelining Explained
Recent questions tagged pipelining
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Made Easy Class Question.
Consider the 4-stages(S1, S2, S3, S4) pipeline where different instructions are spending different cycles at different stages given below. S1 S2 S3 S4 I1 1 3 1 2 I2 1 1 3 1 I3 2 1 1 2 I4 1 1 1 2 (a) How many cycles are required to complete the ... ;= n; i++) { I1; I2; I3; I4; } The output of the instruction "I2" will be available after _____ cycles for I2.
Consider the 4-stages(S1, S2, S3, S4) pipeline where different instructions are spending different cycles at different stages given below.S1S2S3S4I11312I21131I32112I41112...
sanjeet24
163
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sanjeet24
asked
Mar 5
CO and Architecture
pipelining
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2
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0
answers
2
GATE CSE 2024 | Set 2 | Question: 48
A non-pipelined instruction execution unit operating at $2 \mathrm{GHz}$ takes an average of $6$ cycles to execute an instruction of a program $\text{P}$. The unit is then redesigned to operate on a $5$ ... hazards. The speedup (rounded off to one decimal place) obtained by the pipelined design over the non-pipelined design is ____________.
A non-pipelined instruction execution unit operating at $2 \mathrm{GHz}$ takes an average of $6$ cycles to execute an instruction of a program $\text{P}$. The unit is the...
Arjun
1.8k
views
Arjun
asked
Feb 16
CO and Architecture
gatecse2024-set2
numerical-answers
co-and-architecture
pipelining
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7
votes
1
answer
3
GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 35
Consider a processor with an in-order five-stage pipeline (IF, ID, EX, MEM, and WB) with clock cycle time $10 \mathrm{~ns}$. This processor is executing a program in which $30 \%$ of the instructions are ... is always started and ignored if the branch is taken. What is the throughput (Million instructions per second) of the system?
Consider a processor with an in-order five-stage pipeline (IF, ID, EX, MEM, and WB) with clock cycle time $10 \mathrm{~ns}$. This processor is executing a program in whic...
GO Classes
690
views
GO Classes
asked
Jan 28
CO and Architecture
goclasses2024-mockgate-13
goclasses
co-and-architecture
pipelining
numerical-answers
1-mark
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3
votes
1
answer
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GO Classes Test Series 2024 | Mock GATE | Test 11 | Question: 14
Which kind of data dependence can cause data hazards in a single-core, pipelined, in-order processor? (Mark all that apply.) read-after-write dependence write-after-read dependence write-after-write dependence read-after-read dependence
Which kind of data dependence can cause data hazards in a single-core, pipelined, in-order processor? (Mark all that apply.)read-after-write dependencewrite-after-read de...
GO Classes
589
views
GO Classes
asked
Jan 13
CO and Architecture
goclasses2024-mockgate-11
goclasses
co-and-architecture
pipelining
multiple-selects
1-mark
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7
votes
1
answer
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GO Classes Test Series 2024 | Mock GATE | Test 11 | Question: 15
An MIPS pipeline has five stages, with a clock cycle of $200 \mathrm{ps}$. Suppose that this MIPS pipeline is redesigned to have four stages, with a clock cycle of $250 \mathrm{ps}$. Assuming an infinite sequence of instructions, what speedup will this new design achieve when compared to the five-stage pipeline?
An MIPS pipeline has five stages, with a clock cycle of $200 \mathrm{ps}$. Suppose that this MIPS pipeline is redesigned to have four stages, with a clock cycle of $250 \...
GO Classes
596
views
GO Classes
asked
Jan 13
CO and Architecture
goclasses2024-mockgate-11
goclasses
numerical-answers
co-and-architecture
pipelining
1-mark
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0
votes
2
answers
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Classic RISC Pipeline
In which stage of the classic RISC pipeline, operand is fetched. Is it in Instruction Decode or Execute (ALU) stage?
In which stage of the classic RISC pipeline, operand is fetched. Is it in Instruction Decode or Execute (ALU) stage?
prasoon054
196
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prasoon054
asked
Jan 7
CO and Architecture
pipelining
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0
votes
1
answer
7
ISRO 2024
An instruction pipeline can be implemented by means of LIFO buffer FIFO buffer Stack None of the above
An instruction pipeline can be implemented by means ofLIFO bufferFIFO bufferStackNone of the above
Ramayya
333
views
Ramayya
asked
Jan 7
CO and Architecture
isro-2024
co-and-architecture
pipelining
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0
votes
1
answer
8
Made easy, computer architecture and orgnaization advance level Q60
RahulVerma3
187
views
RahulVerma3
asked
Jan 1
CO and Architecture
pipelining
co-and-architecture
made-easy-test-series
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1
votes
1
answer
9
Made Easy test series
Abhishek3301
406
views
Abhishek3301
asked
Dec 5, 2023
CO and Architecture
made-easy-test-series
co-and-architecture
pipelining
gate-preparation
goclasses
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0
votes
1
answer
10
Operand Forwarding [ Self Doubt }
I have a Self doubt question on Operand Forwarding . The data forwarded should be done in EX-EX stage or Mem-EX ? Which one to follow and when ? Using EX-EX we require less no. of cycles.
I have a Self doubt question on Operand Forwarding . The data forwarded should be done in EX-EX stage or Mem-EX ? Which one to follow and when ?Using EX-EX we require les...
Deepak9000
258
views
Deepak9000
asked
Nov 5, 2023
CO and Architecture
pipelining
co-and-architecture
operand-forwarding
data-dependency
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0
votes
2
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11
pipelining hazard
Consider a 5-stage pipelined processor with stages - Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MA) and Write Back (WB). All stages except Memory Access takes 1 clock cycle each for all instructions. Memory access takes 3 clock cycles for instruction LOAD. How many ... (R4) ; R3 ← [4 + [R4]] I3 : SUB R5, R3, R4 ; R5 ← R3 - R4 ans is 14 bt how?
Consider a 5–stage pipelined processor with stages – Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MA) and Write Back (WB). All stages...
24aaaa23
441
views
24aaaa23
asked
Oct 3, 2023
Operating System
operating-system
pipelining
effective-memory-access
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0
votes
1
answer
12
EXAMS 2023 CO and Architecture
A RISC machine has a clock period of 50ns. 20% of its commands are LOAD and STORE commands. On average, 50% NO-OP instructions and 50% useful instructions are placed in the delay slots of these instructions. In the new model of the machine ... instruction, and only 20% of all delay slots are filled with useful instructions. Which machine is faster and by how much?
A RISC machine has a clock period of 50ns. 20% of its commands are LOAD and STORE commands. On average, 50% NO-OP instructions and 50% useful instructions are placed in t...
Greepes
443
views
Greepes
asked
Sep 19, 2023
CO and Architecture
co-and-architecture
pipelining
combinatory
exam-stress
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0
votes
1
answer
13
COA | Branch Delays
Consider the following sequence of instructions for a pipelined processor with one branch delay slot: I1 LABEL: ADD R3 ← R3 + 1 I2 DIV R2 ← R2/R6 I3 SUB R1 ← R2-1 I4 If R1≤0 then BRANCH to LABEL I5 SUB R3 ← R3-R7 Which of the following is true after ... now label pointing to I3. C) I2 shifted to branch delay slot. D) I1 shifted to branch delay slot and now LABEL pointing to I2.
Consider the following sequence of instructions for a pipelined processor with one branch delay slot: I1 LABEL: ADD R3 ← R3 + 1I2 DIV R2 ← R2/R6I3 ...
paarthsinghrathore
390
views
paarthsinghrathore
asked
Aug 18, 2023
CO and Architecture
made-easy-test-series
co-and-architecture
pipelining
branch-conditional-instructions
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0
votes
1
answer
14
Unacadmey book
If we have a non pipeline processor which has a cycle time of 40 ns and average CPI of 5.4 .Assuming a 5 stage pipeline model calculate the speed up of pipeline over non pipeline processor.
If we have a non pipeline processor which has a cycle time of 40 ns and average CPI of 5.4 .Assuming a 5 stage pipeline model calculate the speed up of pipeline over non ...
Praful jha
470
views
Praful jha
asked
Jul 8, 2023
CO and Architecture
co-and-architecture
pipelining
speedup
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0
votes
1
answer
15
scientist B cpcb exam 2023. computer-science engineering. Need help to solved! Urgent!
We have a combinational block [implementing an operation] that can be divided into 3 partitions as 70ps, 40ps and 65ps. The system throughput can be improved using pipelining. Assuming that we are given one ... is 20 ps, the maximum achievable throughput (in GOPS, rounded to 2 decimal places) is _____________.
We have a combinational block [implementing an operation] that can be divided into 3 partitions as 70ps, 40ps and 65ps. The system throughput can be improved using pipel...
Jai Singh
369
views
Jai Singh
asked
Jun 22, 2023
CO and Architecture
pipelining
co-and-architecture
+
–
0
votes
1
answer
16
Ace Test Series | Computer Organistaion
A pipelined processor with a separate instruction & data cache has 5- stages, the cycle time 30 nano sec. It can start a new instruction on every cycle when there were no hazards. It is used with copy- back data cache with a block size of one - ... store which only result hazards. What is the throughout of CPU. a) 31 MIPS b) 24 MIPS c) 48 MIPS d) 10 MIPS
A pipelined processor with a separate instruction & data cache has 5- stages, the cycle time 30 nano sec. It can start a new instruction on every cycle when there were no...
none30
329
views
none30
asked
Jun 12, 2023
CO and Architecture
ace-test-series
co-and-architecture
pipelining
throughput
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–
1
votes
1
answer
17
pipeline
6. A processor X1 operating at 2 GHz has a standard 5-stage RISC instruction pipeline having a base CPI (cycles per instruction) of one without any pipeline hazards. For a given program P that has 30% branch instructions, control hazards incur 2 cycles stall for every branch. ... , the speed up (rounded off to two decimal places) obtained by X2 over X1 in executing P is ?. (GATE CSE 2022)
6. A processor X1 operating at 2 GHz has a standard 5-stage RISC instruction pipeline having a base CPI (cycles per instruction) of one without any pipeline hazards. For ...
Veeresh Badiger
484
views
Veeresh Badiger
asked
Mar 5, 2023
CO and Architecture
pipelining
+
–
0
votes
0
answers
18
pipeline
6. A processor X1 operating at 2 GHz has a standard 5-stage RISC instruction pipeline having a base CPI (cycles per instruction) of one without any pipeline hazards. For a given program P that has 30% branch instructions, control hazards incur 2 cycles stall for every branch. ... , the speed up (rounded off to two decimal places) obtained by X2 over X1 in executing P is ?. (GATE CSE 2022)
6. A processor X1 operating at 2 GHz has a standard 5-stage RISC instruction pipeline having a base CPI (cycles per instruction) of one without any pipeline hazards. For ...
Veeresh Badiger
354
views
Veeresh Badiger
asked
Mar 5, 2023
CO and Architecture
pipelining
+
–
9
votes
4
answers
19
GATE CSE 2023 | Question: 23
Consider a $3$-stage pipelined processor having a delay of $10 \mathrm{~ns}$ (nanoseconds), $20 \mathrm{~ns}$, and $14 \mathrm{~ns},$ for the first, second, and the third stages, respectively. Assume that there is no other ... instruction is fetched every cycle. The total execution time for executing $100$ instructions on this processor is _____________ $\mathrm{ns}.$
Consider a $3$-stage pipelined processor having a delay of $10 \mathrm{~ns}$ (nanoseconds), $20 \mathrm{~ns}$, and $14 \mathrm{~ns},$ for the first, second, and the third...
admin
9.5k
views
admin
asked
Feb 15, 2023
CO and Architecture
gatecse-2023
co-and-architecture
pipelining
numerical-answers
1-mark
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