Recent questions tagged pipelining / GATE Overflow for GATE CSE

6 votes

1 answer

121

GATE Overflow Test Series | Computer Organization and Architecture | Test 1 | Question: 15
A non-pipeline processor $X$ has a clock frequency of $2.5\;GHz$ and an average CPI of $3.$ Processor $Y$ an improved version of $X,$ is designed with $5$ stage linear instruction pipeline. However, ... the processors the speedup of processor $Y$ as compared to $X$ is ________ (rounded to $1$ decimal points)

A non-pipeline processor $X$ has a clock frequency of $2.5\;GHz$ and an average CPI of $3.$ Processor $Y$ an improved version of $X,$ is designed with $5$ stage linear in...

gatecse

304 views

gatecse asked Aug 3, 2020

3 votes

1 answer

122

GATE Overflow Test Series | Computer Organization and Architecture | Test 1 | Question: 17
An instruction pipeline consists of $5$ stages - Fetch (F), Decode (D), Execute (E), Memory (M) and Write (W). The four instruction in an instruction sequence need these stages for different number of ... The number of clock cycles needed to perform these four instructions is ______

An instruction pipeline consists of $5$ stages - Fetch (F), Decode (D), Execute (E), Memory (M) and Write (W). The four instruction in an instruction sequence need these ...

gatecse

236 views

gatecse asked Aug 3, 2020

13 votes

1 answer

123

GATE Overflow Test Series | Computer Organization and Architecture | Test 1 | Question: 18
Consider a $5$-stage pipeline - IF (Instruction Fetch), ID (Instruction Decode and register read), EX (Execute), MEM (Memory) and WB (Write Back). All register reads take place in the second phase of a clock cycle and ... read) hazards by $B$ and WAW (Write after write) hazards by $C,$ then $A+B+C = $_____

Consider a $5$-stage pipeline - IF (Instruction Fetch), ID (Instruction Decode and register read), EX (Execute), MEM (Memory) and WB (Write Back). All register reads take...

gatecse

776 views

gatecse asked Aug 3, 2020

6 votes

1 answer

124

GATE Overflow Test Series | Computer Organization and Architecture | Test 1 | Question: 19
Suppose the functions $A$ and $B$ can be computed in $6$ and $4$ nanoseconds by functional units $U_A$ and $U_B$, respectively. Given two instances of $U_A$ and three instances of $U_B$, ... . Ignoring all other delays, the minimum time required to complete this computation (in nanoseconds) is _______

Suppose the functions $A$ and $B$ can be computed in $6$ and $4$ nanoseconds by functional units $U_A$ and $U_B$, respectively. Given two instances of $U_A$ and three ins...

gatecse

501 views

gatecse asked Aug 3, 2020

6 votes

2 answers

125

GATE Overflow Test Series | Computer Organization and Architecture | Test 1 | Question: 20
Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction(FI), Decode Instruction(DI), Fetch Operand(FO), Execute instruction(EI) and Write Operand(WO). The stage delays ... the execution of this program, the time(in ns) needed to complete the program is ________

Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction(FI), Decode Instruction(DI), Fetch Operand(FO), Execute instruction(EI)...

gatecse

460 views

gatecse asked Aug 3, 2020

5 votes

2 answers

126

GATE Overflow Test Series | Computer Organization and Architecture | Test 1 | Question: 29
The Fetch, Decode, Execute, Memory and Write Back stages of a processor have the latencies $300ps, 300ps, 350ps, 500ps$ and $110ps$ respectively. What is the ratio of the throughputs of a ... for the register between the pipeline stages and a non-pipelined implementation (correct to one decimal place)?

The Fetch, Decode, Execute, Memory and Write Back stages of a processor have the latencies $300ps, 300ps, 350ps, 500ps$ and $110ps$ respectively. What is the ratio of the...

gatecse

356 views

gatecse asked Aug 3, 2020

3 votes

2 answers

127

NIELIT 2017 OCT Scientific Assistant A (IT) - Section B: 18
A pipeline is having speed up factor as $10$ and operating with efficiency of $80\%.$ What will be the number of stages in the pipeline? $10$ $8$ $13$ None

A pipeline is having speed up factor as $10$ and operating with efficiency of $80\%.$ What will be the number of stages in the pipeline?$10$$8$$13$None

admin

966 views

admin asked Apr 1, 2020

4 votes

3 answers

128

NIELIT 2016 DEC Scientist B (CS) - Section B: 23
A nonpipeline system taken $50ns$ to process a task. The same task can be processed in a six-segment pipeline with a clock cycle of $10ns.$ Determinant the speedup ration of the pipeline for $100$ tasks. What is the maximum speedup that can be achieved? $4.90,5$ $4.76,5$ $3.90,5$ $4.30,5$

A nonpipeline system taken $50ns$ to process a task. The same task can be processed in a six-segment pipeline with a clock cycle of $10ns.$ Determinant the speedup ration...

admin

2.3k views

admin asked Mar 31, 2020

0 votes

3 answers

129

NIELIT 2017 July Scientist B (CS) - Section B: 23
Comparing the time $T1$ taken for a single instruction on a pipelined CPU, with time $T2$ taken on a non-pipelined but identical CPU, we can say that ______ ? $T1=T2$ $T1>T2$ $T1<T2$ $T1$ is $T2$ plus time taken for one instruction fetch cycle

Comparing the time $T1$ taken for a single instruction on a pipelined CPU, with time $T2$ taken on a non-pipelined but identical CPU, we can say that ______ ?$T1=T2$$T1>T...

admin

1.1k views

admin asked Mar 30, 2020

4 votes

5 answers

130

NIELIT 2017 DEC Scientist B - Section B: 13
Consider a non-pipelined machine with $6$ stages; the lengths of each stage are $\text{20ns, 10ns, 30ns,25ns, 40 ns}$ and $\text{15ns}$ respectively. Suppose for implementing the pipelining the machine adds $\text{5 ns}$ of overhead to each stage ... What is the speed up factor of the pipelining system (ignoring any hazard impact)? $7$ $14$ $3.11$ $6.22$

Consider a non-pipelined machine with $6$ stages; the lengths of each stage are $\text{20ns, 10ns, 30ns,25ns, 40 ns}$ and $\text{15ns}$ respectively. Suppose for implemen...

admin

5.1k views

admin asked Mar 30, 2020

0 votes

3 answers

131

NIELIT 2017 DEC Scientist B - Section B: 14
We have $10$-stage pipeline, where the branch target conditions are resolved at stage $5$. How many stalls are there for an incorrectly predicted branch? $5$ $6$ $7$ $4$

We have $10$-stage pipeline, where the branch target conditions are resolved at stage $5$. How many stalls are there for an incorrectly predicted branch?$5$$6$$7$$4$

admin

2.0k views

admin asked Mar 30, 2020

0 votes

1 answer

132

UGC NET CSE | December 2004 | Part 2 | Question: 47
The processing speeds of pipeline segments are usually : Equal Unequal Greater None of these

The processing speeds of pipeline segments are usually :EqualUnequalGreaterNone of these

go_editor

864 views

go_editor asked Mar 27, 2020

25 votes

4 answers

133

GATE CSE 2020 | Question: 43
Consider a non-pipelined processor operating at $2.5$ GHz. It takes $5$ clock cycles to complete an instruction. You are going to make a $5$- stage pipeline out of this processor. Overheads associated with pipelining force you to ... , the speedup achieved by the pipelined processor over the non-pipelined processor (round off to $2$ decimal places) is_____________.

Consider a non-pipelined processor operating at $2.5$ GHz. It takes $5$ clock cycles to complete an instruction. You are going to make a $5$- stage pipeline out of this p...

Arjun

16.5k views

Arjun asked Feb 12, 2020

9 votes

1 answer

134

ISRO2020-6
A non-pipelined CPU has $12$ general purpose registers $(R0,R1,R2, \dots ,R12)$. Following operations are supported $\begin{array}{ll} \text{ADD Ra, Rb, Rr} & \text{Add Ra to Rb and store the result in Rr} \end{array}$ ... $R0,R1$ and $R2$ and contents of these registers must not be modified. $5$ $6$ $7$ $8$

A non-pipelined CPU has $12$ general purpose registers $(R0,R1,R2, \dots ,R12)$. Following operations are supported$\begin{array}{ll} \text{ADD Ra, Rb, Rr} & \text{Add Ra...

Satbir

3.5k views

Satbir asked Jan 13, 2020

7 votes

4 answers

135

ISRO2020-7
Consider a $5$- segment pipeline with a clock cycle time $20$ ns in each sub operation. Find out the approximate speed-up ratio between pipelined and non-pipelined system to execute $100$ instructions. (if an average, every five cycles, a bubble due to data hazard has to be introduced in the pipeline) $5$ $4.03$ $4.81$ $4.17$

Consider a $5$- segment pipeline with a clock cycle time $20$ ns in each sub operation. Find out the approximate speed-up ratio between pipelined and non-pipelined system...

Satbir

7.3k views

Satbir asked Jan 13, 2020

0 votes

0 answers

136

Andrew S. Tanenbaum (OS) Edition 4 Exercise 5 Question 11 (Page No. 430)
A computer has a three-stage pipeline as shown in Fig. 1-7(a). On each clock cycle, one new instruction is fetched from memory at the address pointed to by the PC and put into the pipeline and ... instruction of the interrupt handler is fetched into the pipeline. Does this machine have precise interrupts? Defend your answer.

A computer has a three-stage pipeline as shown in Fig. 1-7(a). On each clock cycle, one new instruction is fetched from memory at the address pointed to by the PC and put...

admin

846 views

admin asked Oct 28, 2019

1 votes

4 answers

137

Andrew S. Tanenbaum (OS) Edition 4 Exercise 1 Question 14 (Page No. 82)
A computer has a pipeline with four stages. Each stage takes the same time to do its work, namely, $1$ nsec. How many instructions per second can this machine execute?

A computer has a pipeline with four stages. Each stage takes the same time to do its work, namely, $1$ nsec. How many instructions per second can this machine execute?

admin

1.7k views

admin asked Oct 23, 2019

1 votes

1 answer

138

Self Doubt: CO Syllabus
Is pipeline hazards there in the syllabus? And are there any previous year questions from there?

Is pipeline hazards there in the syllabus? And are there any previous year questions from there?

Hirak

586 views

Hirak asked May 23, 2019

0 votes

0 answers

139

PIPELINING.
How to find number of stall cycles and branch penalty & CPI in a branched instruction pipelining?

How to find number of stall cycles and branch penalty & CPI in a branched instruction pipelining?

Ritabrata Dey

399 views

Ritabrata Dey asked May 21, 2019

1 votes

2 answers

140

ISI2018-PCB-CS8
Consider a $5$ ... $\text{(in ns)}$ needed to execute the program.

Consider a $5$-stage instruction pipeline. The stages and the corresponding stage delays are given below.$$\begin{array}{|l|l|}\hline \textbf{Instruction}&\textbf{Stage d...

akash.dinkar12

1.3k views

akash.dinkar12 asked May 12, 2019

0 votes

0 answers

141

Subject Topic- CO & Architecture
how is this executed MOV X, R ; μ[x]←R using IF, ID, OF,PO, WB

how is this executed MOV X, R ; μ[x]←R using IF, ID, OF,PO, WB

Doraemon

352 views

Doraemon asked Mar 18, 2019

1 votes

1 answer

142

Pipeline
Please cite some useful resources where lots of problems are based on pipeline,illustrating every kind of problems can be asked in GATE

Please cite some useful resources where lots of problems are based on pipeline,illustrating every kind of problems can be asked in GATE

s_dr_13

662 views

s_dr_13 asked Mar 8, 2019

2 votes

2 answers

143

Self Doubt
How many cycle required when pipelining and operand loading is used? R1<-R2+R3 R4<-R1+M[100] Value at M[100]=7 There are 5 phases: F->TO FETCH D->TO DECODE AND OPERAND READ E->EXECUTE M->MEMORY ACCESS W->WRITE BACK Each phase takes 1Cycle .

How many cycle required when pipelining and operand loading is used?R1<-R2+R3R4<-R1+M[100]Value at M[100]=7There are 5 phases:F->TO FETCHD->TO DECODE AND OPERAND READE->...

DIYA BASU

628 views

DIYA BASU asked Feb 18, 2019

1 votes

0 answers

144

Self Doubt
When using pipelining can we have an arrangement like this? I1 F1 D1 E1 M1 W1 I2 F2 ______ ____ _____ D2 E2 M2 W2 I3 F3 D3 E3 M3 W3 Where I2 has Read after write dependency on I1 and operand forwarding is not used. I3 is independent of I1 and I2 F=INSTRUCTION FETCH. D=DECODING AND READING THE OPERANDS FROM THE REGISTER E=EXECUTE M=MEMORY OPERATION W=WRITE BACK

When using pipelining can we have an arrangement like this?I1F1D1E1M1W1 I2 F2_______________D2E2M2W2 I3 F3D3E3M3W3 Where I2 has Read after write dependency on I1...

DIYA BASU

529 views

DIYA BASU asked Feb 18, 2019

0 votes

1 answer

145

GATE-2000
Comparing the time T1 taken for a single instruction on a pipelined CPU with time T2 taken on a non pipelined but identical CPU, we can say that (A) T1 <= T2 (B) T1 >= T2 (C) T1 < T2 (D) T1 is T2 plus the time taken for one ... instruction would take to execute in a non-pipelined system as it has only one unit.(I AM COMPARING ONLY THE TIME TAKEN BY A SINGLE INSTRUCTION).

Comparing the time T1 taken for a single instruction on a pipelined CPU with time T2 taken on a non pipelined but identical CPU, we can say that(A) T1 <= T2 (B) T1 >= T...

DIYA BASU

1.1k views

DIYA BASU asked Feb 10, 2019

0 votes

1 answer

146

ACE CBT 2018
An instruction pipelined processor has five stages namely, instruction fetch (F), instruction decode (D), Instruction execution (E), memory Access for operand (M) and write Back (W) with stage latencies of 1 ns, 2ns, 2 ns, 1 ns, 1 ns respectively. To gain ... (in ns) using new design over old design is __________. I am getting 99 but the answer provided is 96. Can you please verify.

An instruction pipelined processor has five stages namely, instruction fetch (F), instruction decode(D), Instruction execution (E), memory Access for operand (M) and writ...

OneZero

626 views

OneZero asked Jan 24, 2019

0 votes

0 answers

147

Made easy test series pipelining
Consider a 5 stage pipeline with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Write Back (WB) and Memory Access (MA) having latencies (in ns) 3,8, 5, 6 and 4 respectively. What is average CPl of non-pipeline CPU when speed up achieved by to pipeline is 4? A. 1.33 B. 1.76 C. 1.14 D. 1.66

Consider a 5 stage pipeline with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Write Back (WB) and Memory Access (MA) having latencies (in ns) 3,8, 5, 6 ...

Ram Swaroop

774 views

Ram Swaroop asked Jan 23, 2019

0 votes

0 answers

148

Made Easy
True or False:In a uniform delay pipeline stage the execution time of a single instruction is equal to the time for execution of the instruction in non pipelined manner. Shouldn’t it be false as thought each stage has uniform delay there would be additional buffer delay after each stage of the pipeline so shouldnt it be that it is not equal i.e it is more????

True or False:In a uniform delay pipeline stage the execution time of a single instruction is equal to the time for execution of the instruction in non pipelined manner.S...

anjali007

428 views

anjali007 asked Jan 23, 2019

0 votes

1 answer

149

CAO ME
Consider a pipeline processor with 5 stages, Instruction Fetch (IF). Instruction Decode and Operand Fetch (ID), Operation performed (OP). Data memory access (MA) and Write back (WB). The IF, ID, MA and WB stages takes 1 clock cycle each ... for MUL instruction. The minimum number of clock cycles are needed to complete following sequence of instruction if operand forwarding is used ________.

Consider a pipeline processor with 5 stages, Instruction Fetch (IF). Instruction Decode and Operand Fetch (ID), Operation performed (OP). Data memory access (MA) and Writ...

balchandar reddy san

526 views

balchandar reddy san asked Jan 20, 2019

1 votes

0 answers

150

Instruction Pipeline
Consider an instruction pipeline with five stages , it allows overlapping of all instructions except branch type. Let there are 20% branch instructions and pipeline is operated with 800 megahertz. 1) what is the speedup? 2) what is average instruction time. 3) what is the time taken for 10 million instructions. 4) what is the throughput.

Consider an instruction pipeline with five stages , it allows overlapping of all instructions except branch type. Let there are 20% branch instructions and pipeline is o...

Nandkishor3939

1.3k views

Nandkishor3939 asked Jan 19, 2019

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