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Pipelining Explained
Recent questions tagged pipelining
1
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0
answers
151
Speedup in coa
In a processor each instruction execution completes in 4 clock cycle with 2.5 gigahertz. The same processor is transformed into a pipelined processor with five stages operated with 2.0 gigahertz what is the speedup achieved.
In a processor each instruction execution completes in 4 clock cycle with 2.5 gigahertz. The same processor is transformed into a pipelined processor with five stages ope...
Nandkishor3939
771
views
Nandkishor3939
asked
Jan 19, 2019
CO and Architecture
pipelining
speedup
co-and-architecture
+
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0
votes
1
answer
152
ME TEST SERIES QUESTION ON PIPELINE
Shankar Kakde
426
views
Shankar Kakde
asked
Jan 16, 2019
CO and Architecture
co-and-architecture
pipelining
speedup
made-easy-test-series
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1
votes
1
answer
153
MadeEasyTest
6 stage pipeline without any branch prediction pipeline cycle time is 4ns used to execute program segment with 20 instruction (i-1 to i-20) i5 is unconditional TOC instruction which transfer the control to i-18.Pipeline target address is available in 4th stage then Program execution time is …..
6 stage pipeline without any branch prediction pipeline cycle time is 4ns used to execute program segment with 20 instruction (i-1 to i-20) i5 is unconditional TOC instru...
Abhisek Tiwari 4
278
views
Abhisek Tiwari 4
asked
Jan 16, 2019
CO and Architecture
co-and-architecture
pipelining
made-easy-test-series
numerical-answers
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1
votes
1
answer
154
Applied Course | Mock GATE | Test 1 | Question: 61
Consider a pipelined processor, which has $5$ stages Fetch, Decode, Execute, memory and Write back with latencies $300 \: ms$, $400 \: ms$, $350 \: ms$, $550 \: ms$ and $100 \: ms$ respectively. What is the latency of an instruction? (Assume ... $1700 \: ms$ $1720 \: ms$ $2750 \: ms$ $2850 \: ms$
Consider a pipelined processor, which has $5$ stages Fetch, Decode, Execute, memory and Write back with latencies $300 \: ms$, $400 \: ms$, $350 \: ms$, $550 \: ms$ and ...
Applied Course
495
views
Applied Course
asked
Jan 16, 2019
CO and Architecture
applied-course-2019-mock1
co-and-architecture
pipelining
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1
votes
1
answer
155
PIPELINING
Consider the following sequence of instructions executed on the five-stage pipelined processor: LW $1, 30($6) ADD $2, $4, $2 ADD $1, $3, $5 SW $2, 20($4) ADD $1, $1, $4 Assuming there is no forwarding, calculate the number of clock cycles needed to execute above program ?
Consider the following sequence of instructions executed on the five-stage pipelined processor:LW $1, 30($6)ADD $2, $4, $2ADD $1, $3, $5SW $2, 20($4)ADD $1, $1, $...
Himanshu Kashyap
760
views
Himanshu Kashyap
asked
Jan 16, 2019
CO and Architecture
pipelining
computer-organisation
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2
votes
1
answer
156
MadeEasy Test Series 2019: CO & Architecture - Pipelining
5 stage pipeline → 3,6,5,8,4 latencies(in ns).What is average CPI of non pipelined CPU when speed up achieved by to pipeline is 4 ? (ans = 1.23)
5 stage pipeline → 3,6,5,8,4 latencies(in ns).What is average CPI of non pipelined CPU when speed up achieved by to pipeline is 4 ? (ans = 1.23)
Satbir
853
views
Satbir
asked
Jan 16, 2019
CO and Architecture
co-and-architecture
pipelining
made-easy-test-series
+
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0
votes
2
answers
157
made easy
A hypothetical 5 stage pipeline processor is designed in which branch is predicted at 3rd stage and each stage takes 1 cycle to compute its tasks. If f is the probability of an instruction being branch instruction then the value of f such that speedup is atleast 3 is____
A hypothetical 5 stage pipeline processor is designed in which branch is predicted at 3rd stage and each stage takes 1 cycle to compute its tasks. If f is the probability...
Harshit Bajpai
1.0k
views
Harshit Bajpai
asked
Jan 14, 2019
CO and Architecture
co-and-architecture
pipelining
speedup
branch-conditional-instructions
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0
votes
0
answers
158
Test series
#Pipelining Please clear my doubt. In a 5 stage pipelining (IF, ID, EX, MA, WB) there are 5 instruction given. Instruction 1 : R2 ← R0 + R1; Instruction 2 : R1 ← R2 - R1; Instruction 3 : R0 ← R2 - R0; Instruction 4 : R2 ← ... My understanding is whenever dependency is there b/w instruction, ID phase of Next instruction will occur after EX phase of previous Instruction. It is correct ?
#PipeliningPlease clear my doubt.In a 5 stage pipelining (IF, ID, EX, MA, WB)there are 5 instruction given.Instruction 1 : R2 ← R0 + R1;Instruction 2 : R1 ← R2 - R1;I...
aditya dhanraj
170
views
aditya dhanraj
asked
Jan 13, 2019
CO and Architecture
co-and-architecture
pipelining
operand-forwarding
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–
0
votes
0
answers
159
madeeasy
Consider a 5 stage pipeline with IF , ID, EX, WB and MA having latencies (in ms) 3,8,5,6,4. What is average CPI of non pipeline CPU when speed up achieved by to pipeline is 4? I think answer is wrong For non pipe line total time = Total number of ... * time for each cycle calculation For pipeline version total time = Total number of instruction * max(3,8,5,6,4) So No role of CPI
Consider a 5 stage pipeline with IF , ID, EX, WB and MA having latencies (in ms) 3,8,5,6,4. What is average CPI of non pipeline CPU when speed up achieved by to pipeline ...
mehul vaidya
299
views
mehul vaidya
asked
Jan 12, 2019
CO and Architecture
co-and-architecture
pipelining
speedup
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0
votes
0
answers
160
ME TEST SERIES DOUBT
A CPU Manufacturer company has two designs p1 and p2 for a synchronous pipeline processor. P1 has 5 pipeline stages with execution times of 3 ns, 4 ns, 3 ns, 2 ns, 4 ns while the design P2 has 6pipeline stage with 3 ns each (execution time). The time that can be saved by P2 over P1 for executing 1000 Instructions is _____________ ns. iam getting answer 997 but they give 1001
A CPU Manufacturer company has two designs p1 and p2 for a synchronous pipeline processor.P1 has 5 pipeline stages with execution times of 3 ns, 4 ns, 3 ns, 2 ns, 4 ns wh...
Deepanshu
336
views
Deepanshu
asked
Jan 11, 2019
CO and Architecture
co-and-architecture
pipelining
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1
votes
4
answers
161
Madeeasy- Types of Dependencies
Please clarify along with the names.
Please clarify along with the names.
Markzuck
1.3k
views
Markzuck
asked
Jan 9, 2019
CO and Architecture
co-and-architecture
data-dependency
data-hazards
pipelining
databases
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0
votes
0
answers
162
Madeeasy COA Ques
Please explain.
Please explain.
Shubham Kumar Gupta
373
views
Shubham Kumar Gupta
asked
Jan 9, 2019
CO and Architecture
co-and-architecture
pipelining
operand-forwarding
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1
votes
3
answers
163
ME TEST SERIES
A hypothetical 5 stage pipeline processor is designed in which branch is predicted at 3rd stage and each stage takes 1 cycle to compute its task. If p is a the probability of an instruction being a branch instruction then the value of p such that speed up is atleast 3 is ________. (Upto 2 decimal places)
A hypothetical 5 stage pipeline processor is designed in which branch is predicted at 3rd stage and each stage takes 1 cycle to compute its task. If p is a the probabi...
himgta
1.6k
views
himgta
asked
Jan 9, 2019
CO and Architecture
co-and-architecture
pipelining
made-easy-test-series
+
–
0
votes
1
answer
164
How many stall cycles are caused due to each incorrect branch prediction?
The title says it all: How many stall cycles are caused due to each incorrect branch prediction? Additional details you might need: Branch is executed in execution stage of pipeline (but will love to know what happens when branch is executed in decode stage too)
The title says it all: How many stall cycles are caused due to each incorrect branch prediction?Additional details you might need:Branch is executed in execution stage of...
Raj Singh 1
752
views
Raj Singh 1
asked
Jan 9, 2019
CO and Architecture
co-and-architecture
pipelining
stall
branch-conditional-instructions
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0
votes
0
answers
165
made_easy
garimanand
162
views
garimanand
asked
Jan 6, 2019
CO and Architecture
co-and-architecture
pipelining
speedup
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–
0
votes
0
answers
166
ME OTS : Pipelining
Consider the following statements (I) Execution time for single instruction on six stage pipelined CPU is less than or equal to identical non- pipelined CPU. (ii) In a uniform delay pipeline execution time for a single instruction is equal to the ... if stage delay exist then for single execution, pipeline time will not be equal. Hence 2nd statement wont be true always.
Consider the following statements(I) Execution time for single instruction on six stagepipelined CPU is less than or equal to identical non-pipelined CPU.(ii) In a unifor...
HeadShot
1.1k
views
HeadShot
asked
Jan 5, 2019
CO and Architecture
co-and-architecture
pipelining
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–
0
votes
0
answers
167
UPPCL AE 2018:50
Assume that we test the performance of two processors, $\text{P}_{1}$ and $\text{P}_{2},$ on a program. We find the following about each: Processor $\text{P}_{1}$ has a $\text{CPI}$ of $2$ and executes $2$ billion instructions per ... $\text{B}$ Not enough information to tell Processor $\text{A}$ They have equal performance
Assume that we test the performance of two processors, $\text{P}_{1}$ and $\text{P}_{2},$ on a program. We find the following about each:Processor $\text{P}_{1}$ has a $\...
admin
260
views
admin
asked
Jan 5, 2019
CO and Architecture
uppcl2018
co-and-architecture
pipelining
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–
0
votes
0
answers
168
UPPCL AE 2018:44
In an instruction execution pipeline, the earliest that the instruction $\text{TLB}$ and data $\text{TLB}$ can be accessed are Memory stage and memory stage respectively Memory stage and execute stage respectively Fetch stage and fetch stage respectively Fetch stage and memory stage respectively
In an instruction execution pipeline, the earliest that the instruction $\text{TLB}$ and data $\text{TLB}$ can be accessed areMemory stage and memory stage respectivelyMe...
admin
213
views
admin
asked
Jan 5, 2019
CO and Architecture
uppcl2018
co-and-architecture
pipelining
+
–
0
votes
1
answer
169
Computer Org and A1
Total: n instruction Total conditional statement probability :p and True condition probability:q i)Branch is known at end of t satge Effective CPI = [npq*(t+1) + (n-npq)*1)]/n OR ii) Penality is t stall cycle same i.e Effective CPI = [npq*(t+1) + (n-npq)*1)]/n OR iii) Effective CPI= 1+ stall freq*stall penality =1+pq*t am i correct???
Total: n instruction Total conditional statement probability :p and True condition probability:qi)Branch is known at end of t satgeEffective CPI = [npq*(t+1) + (n-npq)*1)...
Abhisek Tiwari 4
281
views
Abhisek Tiwari 4
asked
Jan 5, 2019
CO and Architecture
co-and-architecture
pipelining
+
–
0
votes
2
answers
170
Data forwarding in pipelining
Data forwarding is used to avoid which type of conflict?? (1) RAW (2) WAR (3) WAW (4) RAR
Data forwarding is used to avoid which type of conflict??(1) RAW(2) WAR(3) WAW(4) RAR
Abhilash Mishra
1.2k
views
Abhilash Mishra
asked
Jan 2, 2019
CO and Architecture
pipelining
co-and-architecture
operand-forwarding
data-dependency
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–
1
votes
2
answers
171
Speed up factor
Pipeline system has 4 stages and each stage takes 10ns. 30% instructions are branch instructions .each branch instruction introduces delay of 3 cycle. What is speed up factor compare to same non pipelines, If there are 1000 instructions.
Pipeline system has 4 stages and each stage takes 10ns.30% instructions are branch instructions .each branch instruction introduces delay of 3 cycle. What is speed up fac...
Alina
2.9k
views
Alina
asked
Jan 1, 2019
CO and Architecture
co-and-architecture
speedup
pipelining
+
–
0
votes
1
answer
172
Pipelining
Why pipelining cannot operate at its maximum theoretical speed? Maximum theoretical is when we say that it takes same time to process an instruction in pipeline and non pipeline circuit. So why pipelining cannot operate at its maximum theoretical speed?
Why pipelining cannot operate at its maximum theoretical speed?Maximum theoretical is when we say that it takes same time to process an instruction in pipeline and non pi...
Alina
492
views
Alina
asked
Dec 31, 2018
CO and Architecture
co-and-architecture
pipelining
+
–
0
votes
1
answer
173
Avoiding pipeline Hazards
Please Confirm.
Please Confirm.
smsubham
449
views
smsubham
asked
Dec 27, 2018
CO and Architecture
pipelining
hazards
co-and-architecture
data-hazards
data-dependency
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–
1
votes
1
answer
174
GATE Overflow | Mock GATE | Test 1 | Question: 61
A $5$ stage pipeliine is used to overlap all the instructions except the branch instructions. The target of the branch can't be fetched till the current instruction is completed. What is the Throughput (in MIPS) of the system if $20\%$ of the ... The pipeline clock rate is $0.1 \: GHz$. Branch penalty is $4$ cycles. (Upto $2$ decimal place).
A $5$ stage pipeliine is used to overlap all the instructions except the branch instructions. The target of the branch can't be fetched till the current instruction is co...
Ruturaj Mohanty
1.1k
views
Ruturaj Mohanty
asked
Dec 27, 2018
CO and Architecture
go-mockgate-1
numerical-answers
pipelining
co-and-architecture
+
–
0
votes
1
answer
175
Self doubt
If the time taken by a task to get completed is same in the pipeline and non pipeline circuits, then how the time taken to complete the task in non pipeline = k* time taken to complete the task in pipeline where k is no. of segments in the pipeline?
If the time taken by a task to get completed is same in the pipeline and non pipeline circuits, then how the time taken to complete the task in non pipeline = k* time ta...
Nivedita Singh
360
views
Nivedita Singh
asked
Dec 27, 2018
CO and Architecture
co-and-architecture
pipelining
+
–
0
votes
1
answer
176
ACE-FT
Prateek Raghuvanshi
400
views
Prateek Raghuvanshi
asked
Dec 25, 2018
CO and Architecture
co-and-architecture
pipelining
+
–
1
votes
1
answer
177
ME test series
Consider a pipeline 'x', consist of 5 stages named as IF, ID, OF, EX and WB with the respective stage delays of 2 ns, 6 ns, 5 ns, 8 ns and 1 ns. The alternative pipeline 'y' contain the same number of stages but EX stage is divided ... the instructions which are memory based instructions, what is the ratio of speedup of x to speedup of y? 0.727 0.902 0.665 0.825
Consider a pipeline 'x', consist of 5 stages named as IF, ID, OF, EX and WB with the respective stage delays of 2 ns, 6 ns, 5 ns, 8 ns and 1 ns. The alternative pipeline ...
newdreamz a1-z0
736
views
newdreamz a1-z0
asked
Dec 25, 2018
CO and Architecture
computer
co-and-architecture
pipelining
speedup
+
–
0
votes
2
answers
178
MadeEasy Test Series: CO & Architecture - Pipelining
here why to take stall at the highlighted cell as its OPERAND FORWARDING and unless mentioned its EX-EX and its being followed without stall also, please clarify how to understand where Operand Forwarding is to be applied in such generalized cases., Thanks in advance :)
here why to take stall at the highlighted cell as its OPERAND FORWARDING and unless mentioned its EX-EX and its being followed without stall also, please clarify how to u...
Markzuck
951
views
Markzuck
asked
Dec 25, 2018
CO and Architecture
co-and-architecture
pipelining
made-easy-test-series
operand-forwarding
+
–
0
votes
0
answers
179
CO pipelining
consider a 4-stage pipeline (IF, ID, EX, WB) used to execute the following code. All the instructions are spending 1 cycle in all the stags but MUL takes 4 cycles. Div takes 3 cycles in EX stages. The pipeline uses operand forwarding as an optimization a- how many cycles are required to complete ... ? I1 : MUL r0 , r1 , r2 I2 : DIV r3 , r1 , r2 I3: SUB r4, r3, r2 I4: ADD r5, r4, r1
consider a 4-stage pipeline (IF, ID, EX, WB) used to execute the following code. All the instructions are spending 1 cycle in all the stags but MUL takes 4 cycles. Div ta...
hitendra singh
944
views
hitendra singh
asked
Dec 24, 2018
CO and Architecture
co-and-architecture
pipelining
operand-forwarding
+
–
1
votes
1
answer
180
Made easy
abhishekmehta4u
753
views
abhishekmehta4u
asked
Dec 22, 2018
CO and Architecture
co-and-architecture
pipelining
+
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