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Pipelining Explained
Recent questions tagged pipelining
5
votes
2
answers
91
Made Easy Test Series
Consider a pipeline consist of 5 stages named as IF, ID, OF, EX and WB with the respective stage delays of 2 ns, 6 ns, 5 ns, 8 ns and 1 ns. The alternative pipeline y' contain the same number of stages but EX stage is divided into 2 ... the program contain 20% of the instructions which are memory based instructions, what is the ratio of speed-up of x to speed-up of y?
Consider a pipeline consist of 5 stages named as IF, ID, OF, EX and WB with the respective stage delays of 2 ns, 6 ns, 5 ns, 8 ns and 1 ns. The alternative pipeline ‘y...
LRU
669
views
LRU
asked
Jan 20, 2022
CO and Architecture
made-easy-test-series
computer-architecture
pipelining
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4
votes
2
answers
92
Made Easy Test Series
Consider 5 stage pipelined processor has instruction fetch (IF), Instruction decode (ID), Operand fetch (OF), Perform operation (PO) and Write operand (WB) stages. The IF, ID, OF and WB stages takes 1 clock cycle each for any ... instructions respectively. How many clock cycles needed to execute the above sequence of instruction, where operand forwarding from PO to PO?
Consider 5 stage pipelined processor has instruction fetch (IF), Instruction decode (ID), Operand fetch (OF), Perform operation (PO) and Write operand (WB) stages. The IF...
LRU
554
views
LRU
asked
Jan 20, 2022
CO and Architecture
made-easy-test-series
computer-architecture
pipelining
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–
1
votes
1
answer
93
Applied Test Series
Consider the following sequence of instructions: LOAD R4, 0(R8) AND R1, R5, R2 OR R1, R1, R3 OR R2, R2, R7 ADD R3, R2, R1 STORE R3, 0(R8) Number of cycles required to complete the given sequence of instructions in a 5 stage (IF, ID, EX, Mem, WB) RISC processor with operand forwarding_____
Consider the following sequence of instructions: LOAD R4, 0(R8) AND R1, R5, R2 OR R1, R1, R3 OR R2, R2, R7 ADD R3, R2, R1 STORE R3, 0(R8) Number of cycles required to com...
LRU
544
views
LRU
asked
Jan 8, 2022
CO and Architecture
test-series
computer-architecture
pipelining
data-hazards
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–
1
votes
1
answer
94
Applied Test Series
Consider the following sequence of instructions Add #20,R0,R1 Mul #3,R2,R3 And # ... fetch(other stages also) requires only one clock cycle. Number of cycles required to complete the given sequence of instructions are_____
Consider the following sequence of instructions Add #20,R0,R1 Mul #3,R2,R3 And #$3A,R2,R4 Add R0, R2, R5 In all instructions, the destination operand is given last. Init...
LRU
888
views
LRU
asked
Jan 8, 2022
CO and Architecture
test-series
computer-architecture
pipelining
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–
0
votes
2
answers
95
Self doubt Pipelining
Consider a pipeline processor with 5 stages S1 to S5. We want to execute the following loops: while(i<=1) {I1,I2,I3,I4} where i=0. Time (ns) taken by the instruction I1 to I4 for stages S1 to S5 are given below: S1 S2 S3 S4 S5 I1 1 1 2 1 1 I2 1 2 1 1 1 I3 1 2 2 1 1 I4 2 1 2 1 1 Output of I4 will be available at _____.
Consider a pipeline processor with 5 stages S1 to S5. We want to execute the following loops:while(i<=1) {I1,I2,I3,I4} where i=0. Time (ns) taken by the instruction I1 to...
Divyanshu Shukla
431
views
Divyanshu Shukla
asked
Jan 6, 2022
CO and Architecture
pipelining
co-and-architecture
self-doubt
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0
votes
2
answers
96
speedup in pipelining made easy & nptel
Which approach is correct? ASSIGNMENT LINK :-- https://nptel.ac.in/content/storage2/courses/106105163/ASSIGNMENT-SOLUTION-WEEK11.pdf nptel assignment q-1 Caption
Which approach is correct?ASSIGNMENT LINK : https://nptel.ac.in/content/storage2/courses/106105163/ASSIGNMENT-SOLUTION-WEEK11.pdfnptel assignment q-1 Caption
farmanahmed888
523
views
farmanahmed888
asked
Jan 6, 2022
CO and Architecture
co-and-architecture
pipelining
speedup
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0
votes
1
answer
97
COA Applied Course
Assume that we are using the classic MIPS five-stage(IF, ID, EX, MEM and WB) integer pipeling.
Assume that we are using the classic MIPS five-stage(IF, ID, EX, MEM and WB) integer pipeling.
Sagar475
418
views
Sagar475
asked
Dec 26, 2021
CO and Architecture
co-and-architecture
pipelining
operand-forwarding
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1
votes
1
answer
98
Test Series: ACE
How to approach this one?
How to approach this one?
ramakrushna
410
views
ramakrushna
asked
Dec 23, 2021
CO and Architecture
ace-test-series
co-and-architecture
test-series
pipelining
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–
0
votes
1
answer
99
Computer System Architecture By M Morris Mano
The floating-point pipeline are implemented with combinational circuits.Suppose that the time delays of the four segments are t1=60ns, t2=70ns, t3=100ns, t4=80ns, and the interface registers have a delay of tr=10ns. Solution: Pipeline floating-point ... t3+t4+tr=320ns Speedup: 320/110=2.9 My Doubt: why register delay is added in non pipeline system?
The floating-point pipeline are implementedwith combinational circuits.Suppose that the time delays of the four segments are t1=60ns, t2=70ns, t3=100ns, t4=80ns, and the ...
Divyanshu Shukla
630
views
Divyanshu Shukla
asked
Dec 16, 2021
CO and Architecture
pipelining
computer-architecture
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–
0
votes
1
answer
100
ISRO | ISRO CS 2020 | Question 6
Consider a 5-segment pipeline with a clock cycle time 20 ns in each sub operation. Find out the approximate speed-up ratio between pipelined and non-pipelined system to execute 100 instructions. (If an average, every five cycles, a bubble due to data hazard has to be introduced in the pipeline.). (A) 5 (B) 4.03 (C) 4.81 (D) 4.17
Consider a 5-segment pipeline with a clock cycle time 20 ns in each sub operation. Find out the approximate speed-up ratio between pipelined and non-pipelined system to e...
ProtonicRED
567
views
ProtonicRED
asked
Dec 14, 2021
CO and Architecture
co-and-architecture
pipelining
speedup
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1
votes
1
answer
101
GATE appliedroots test series
I have 3 doubts in the following solution: Doubt 1: In red colour While I1 is in the Memory-access stage, how can I4 fetch the instruction from the memory? Isn't this a structural dependency problem? Doubt 2: In blue ... operate with register only so the memory-access stage shouldn't happen for these instructions, correct? Solution as per my understanding:
I have 3 doubts in the following solution:Doubt 1: In red colourWhile I1 is in the Memory-access stage, how can I4 fetch the instruction from the memory? Isn't this a str...
Ashutosh_Mishra
483
views
Ashutosh_Mishra
asked
Dec 12, 2021
CO and Architecture
co-and-architecture
pipelining
operand-forwarding
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0
votes
0
answers
102
NPTEL Assignment Question
Consider the following code : Load R1,M Load R2,N CMP R1,R2 JGE END Store [300],R2 END: Store [300],R1 Assume that M=30 and N=25. The above sequence of instructions is to be executed on a pipelined processor with IF , ... instructions. The branch outcome is known after EX stage. Determine the number of clock cycles required for completion of execution of all instructions.
Consider the following code :Load R1,MLoad R2,NCMP R1,R2JGE ENDStore [300],R2END: Store [300],R1 Assume that M=30 and N=25. The above sequence of instructions is to be ex...
rsansiya111
370
views
rsansiya111
asked
Dec 8, 2021
CO and Architecture
co-and-architecture
pipelining
operand-forwarding
nptel-quiz
branch-conditional-instructions
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0
votes
2
answers
103
Gate Applied Course Test Series
A 5-stage(IF,ID, EX, MEM and WB) MIPS pipeline has a register file without forwarding mechanism.How Many NOPs (or bubbles) will you need to add to make this code work correctly Lw $1, 40($6) Add $6,$2, $2 SW $6, 50($1) //$6 → M[$1+50] A)1 B) 2 C)0 D) 3
A 5-stage(IF,ID, EX, MEM and WB) MIPS pipeline has a register file without forwarding mechanism.How Many NOPs (or bubbles) will you need to add to make this code work cor...
Dheeraj Varma
461
views
Dheeraj Varma
asked
Nov 24, 2021
CO and Architecture
pipelining
co-and-architecture
+
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2
votes
2
answers
104
Doubt regarding pipeline
Hi, I have a question like how Load/Store operation behave in pipelining, with or without operand forwarding ?
Hi, I have a question like how Load/Store operation behave in pipelining, with or without operand forwarding ?
Nihal Singh
1.4k
views
Nihal Singh
asked
Oct 26, 2021
CO and Architecture
co-and-architecture
pipelining
+
–
0
votes
1
answer
105
Applied Test Series
Suppose that we are considering an enhancement that runs 10 times faster than the original machine but is usable only 40% of the time. What is the overall speedup gained by incorporating the enhancement.
Suppose that we are considering an enhancement that runs 10 times faster than the original machine but is usable only 40% of the time. What is the overall speedup gained ...
LRU
2.8k
views
LRU
asked
Oct 23, 2021
CO and Architecture
test-series
co-and-architecture
pipelining
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0
votes
0
answers
106
William Stallings - Computer Organization and Architecture D
A computer system contains a main memory of 32KB. It also has a 4KB cache divided into four-lines/set with 64B per line. Assume that the cache is initially empty. The processor fetches words from locations 0, 1, 2, . . . ... from the use of the cache. Assume an LRU policy for block replacement. Show the state of cache at the end.
A computer system contains a main memory of 32KB. It also has a 4KB cache divided into four-lines/set with 64B per line. Assume that thecache is initially empty. The proc...
lucifer069
297
views
lucifer069
asked
Sep 15, 2021
CO and Architecture
co-and-architecture
pipelining
control-unit
least-recently-used
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–
0
votes
0
answers
107
William Stallings - Computer Organization and Architecture D
Consider the following assembly code: Instruction Description LD R1, 45(R2) Read data from memory and store in R1. Memory address is calculated by adding 45 to the content of R2 ADD R7, R1, R5 Add contents of R1 ... Calculate the execution time and compare time that would have required in a non-pipelined processor to run the same program.
Consider the following assembly code:Instruction DescriptionLD R1, 45(R2) Read data from memory and store in R1. Memory address is calculated by adding 45 to the content ...
lucifer069
325
views
lucifer069
asked
Sep 15, 2021
CO and Architecture
co-and-architecture
control-unit
pipelining
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–
0
votes
2
answers
108
UGC NET CSE | December 2019 | Part 2 | Question: 9
A non-pipelined system takes $\text{30ns}$ to process a task. The same task can be processed in a four-segment pipeline with a clock cycle of $\text{10ns}$. Determine the speed up of the pipeline for $100$ tasks. $3$ $4$ $3.91$ $2.91$
A non-pipelined system takes $\text{30ns}$ to process a task. The same task can be processed in a four-segment pipeline with a clock cycle of $\text{10ns}$. Determine the...
soujanyareddy13
1.3k
views
soujanyareddy13
asked
May 12, 2021
Others
ugcnetcse-dec2019-paper2
co-and-architecture
pipelining
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–
23
votes
4
answers
109
GATE CSE 2021 Set 2 | Question: 53
Consider a pipelined processor with $5$ stages, $\text{Instruction Fetch} (\textsf{IF})$, $\text{Instruction Decode} \textsf{(ID)}$, $\text{Execute } \textsf{(EX)}$, $\text{Memory Access } \textsf{(MEM)}$ ... $\textit{Speedup} $ achieved in executing the given instruction sequence on the pipelined processor (rounded to $2$ decimal places) is _____________
Consider a pipelined processor with $5$ stages, $\text{Instruction Fetch} (\textsf{IF})$, $\text{Instruction Decode} \textsf{(ID)}$, $\text{Execute } \textsf{(EX)}$, $\te...
Arjun
15.1k
views
Arjun
asked
Feb 18, 2021
CO and Architecture
gatecse-2021-set2
co-and-architecture
pipelining
instruction-execution
numerical-answers
2-marks
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–
7
votes
2
answers
110
GATE CSE 2021 Set 1 | Question: 53
A five-stage pipeline has stage delays of $150, 120, 150, 160$ and $140$ nanoseconds. The registers that are used between the pipeline stages have a delay of $5$ nanoseconds each. The total time to execute $100$ independent instructions on this pipeline, assuming there are no pipeline stalls, is _______ nanoseconds.
A five-stage pipeline has stage delays of $150, 120, 150, 160$ and $140$ nanoseconds. The registers that are used between the pipeline stages have a delay of $5$ nanoseco...
Arjun
5.9k
views
Arjun
asked
Feb 18, 2021
CO and Architecture
gatecse-2021-set1
co-and-architecture
pipelining
numerical-answers
2-marks
+
–
1
votes
2
answers
111
UGC NET CSE | October 2020 | Part 2 | Question: 7
A non-pipeline system takes $50$ns to process a task. The same task can be processed in six-segment pipeline with a clockcycle of $10$ns. Determine approximately the speedup ratio of the pipeline for $500$ tasks. $6$ $4.95$ $5.7$ $5.5$
A non-pipeline system takes $50$ns to process a task. The same task can be processed in six-segment pipeline with a clockcycle of $10$ns. Determine approximately the spee...
go_editor
2.1k
views
go_editor
asked
Nov 20, 2020
CO and Architecture
ugcnetcse-oct2020-paper2
co-and-architecture
pipelining
+
–
1
votes
1
answer
112
UGC NET CSE | October 2020 | Part 2 | Question: 43
Which of the following statements with respect to $\text{K}$-segment pipelining are true? Maximum speedup that a pipeline can provide is $k$ theoretically It is impossible to achieve maximum speed up $k$ in $k$-segment pipeline All segments in pipeline take same time in ... $\text{(i)}$ and $\text{(iii)}$ only $\text{(i), (ii)}$ and $\text{(iii)}$
Which of the following statements with respect to $\text{K}$-segment pipelining are true?Maximum speedup that a pipeline can provide is $k$ theoreticallyIt is impossible ...
go_editor
1.3k
views
go_editor
asked
Nov 20, 2020
CO and Architecture
ugcnetcse-oct2020-paper2
co-and-architecture
pipelining
+
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