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Recent questions tagged translation-lookaside-buffer
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GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 46
Assume that for a given system, virtual addresses are $40$ bits long and physical addresses are $30$ bits long. The page size is $8$ KB. The Translation Look-aside Buffer (TLB) in the address translation path has $128$ entries. At most ... distinct virtual addresses can be translated without any TLB miss? $2^7$ $2^{20}$ $2^{13}$ $2^8$
Assume that for a given system, virtual addresses are $40$ bits long and physical addresses are $30$ bits long. The page size is $8$ KB. The Translation Look-aside Buffer...
GO Classes
444
views
GO Classes
asked
Jan 28
Operating System
goclasses2024-mockgate-13
goclasses
operating-system
translation-lookaside-buffer
2-marks
+
–
0
votes
1
answer
2
Madeeasy workbook, chapter: Memory management
Consider a k-level paging system along with a TLB. A TLB takes 10ns, and a memory takes 100ns on average. The hit ratio of TLB is equal to 0.8. If it is known that the average memory access time is 70ns, then the value of k is?
Consider a k-level paging system along with a TLB. A TLB takes 10ns, and a memory takes 100ns on average. The hit ratio of TLB is equal to 0.8. If it is known that the av...
Gaurav Padole
681
views
Gaurav Padole
asked
Dec 29, 2022
Operating System
operating-system
paging
translation-lookaside-buffer
memory-management
made-easy-booklet
+
–
1
votes
1
answer
3
DRDO CSE 2022 Paper 2 | Question: 9
Assume that in a certain computer, the virtual addresses are $64$-bit long, the physical addresses are $48$-bit long, and the memory is word-addressable. The page size is $16 \mathrm{KB}$ and the word size is $8 \mathrm{B}$. ... transalation path has $256$ valid entries. At most how many distinct virtual addresses can be translated without any $\text{TLB}$ miss?
Assume that in a certain computer, the virtual addresses are $64$-bit long, the physical addresses are $48$-bit long, and the memory is word-addressable. The page size is...
admin
357
views
admin
asked
Dec 15, 2022
Operating System
drdocse-2022-paper2
operating-system
translation-lookaside-buffer
5-marks
descriptive
+
–
23
votes
2
answers
4
GATE CSE 2022 | Question: 28
Which one of the following statements is $\text{FALSE}?$ The $\text{TLB}$ performs an associative search in parallel on all its valid entries using page number of incoming virtual address. If the virtual address of a word given by $\text{CPU}$ has a ... $\text{V2}$ map to the same value while hashing, then the memory access time of these addresses will not be the same.
Which one of the following statements is $\text{FALSE}?$The $\text{TLB}$ performs an associative search in parallel on all its valid entries using page number of incoming...
Arjun
8.1k
views
Arjun
asked
Feb 15, 2022
Operating System
gatecse-2022
operating-system
memory-management
translation-lookaside-buffer
2-marks
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2
votes
1
answer
5
GATE Overflow Test Series | Mock GATE | Test 6 | Question: 57
A typical program has $30\%$ memory instructions. Assume there are $4\%$ data TLB misses, each requiring $100$ extra cycles to be handled. Also assume that each instruction requires $1$ cycle to execute, TLB access takes $1$ ... miss takes $75$ extra cycles to be handled. How long (in cycles) would it take to execute $1000$ instructions?
A typical program has $30\%$ memory instructions. Assume there are $4\%$ data TLB misses, each requiring $100$ extra cycles to be handled. Also assume that each instructi...
Arjun
256
views
Arjun
asked
Jan 30, 2022
Operating System
go2025-mockgate-6
operating-system
translation-lookaside-buffer
numerical-answers
2-marks
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–
2
votes
3
answers
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Applied Test Series
A computer system has a page size of 1024 bytes and maintains the page table for each process in main memory. The overhead required for doing a lookup in the page table is 500 ns. To reduce this overhead, the computer has a TLB that ... frame mappings. A TLB lookup requires 100ns. Which TLB hit-rate will ensure an average virtual address translation time of exactly 200ns?
A computer system has a page size of 1024 bytes and maintains the page table for each process in main memory. The overhead required for doing a lookup in the page table i...
LRU
843
views
LRU
asked
Jan 11, 2022
Operating System
test-series
operating-system
paging
translation-lookaside-buffer
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0
votes
1
answer
7
Applied Live Test
Given a byte addressable system which implements demand paging, a TLB has 64 entries and the frame size is 4KB. The LAS is 4MB. TLB has a hit ratio of 90% and has an access time of 2 ns. If the main memory access time is 100 ns and page fault is 5%. The page fault service time is given to be 100 ms. The TLB reach for this system given above is _____ B Anyone can help this.
Given a byte addressable system which implements demand paging, a TLB has 64 entries and the frame size is 4KB. The LAS is 4MB. TLB has a hit ratio of 90% and has an acce...
ramakrushna
513
views
ramakrushna
asked
Jan 3, 2022
Operating System
test-series
operating-system
demand-paging
translation-lookaside-buffer
+
–
1
votes
1
answer
8
Applied Practice test
Suppose: TLB lookup time = 20 ns TLB hit ratio = 80% Memory access time = 75 ns PFST = 500,000 ns 50% of the pages are dirty OS uses a single level page table What is the approximated effective access time (EAT) if we assume the page fault rate is 10%? Assume the cost to update the TLB, the page table, and the frame table (if needed) is negligible.
Suppose: TLB lookup time = 20 nsTLB hit ratio = 80%Memory access time = 75 nsPFST = 500,000 ns50% of the pages are dirtyOS uses a single level page tableWhat is the appro...
darshak_devani
834
views
darshak_devani
asked
Oct 18, 2021
Operating System
memory-management
translation-lookaside-buffer
hit-ratio
+
–
5
votes
2
answers
9
GATE Overflow Test Series | Mock GATE | Test 1 | Question: 15
A single level paging scheme uses a Translation Look-aside Buffer (TLB). A TLB-access takes $20$ nanoseconds and the main memory access takes $70$ nanoseconds. If the TLB hit ratio is $90\%$ and there are no page-faults, the effective memory access time (in nanoseconds) is ___________
A single level paging scheme uses a Translation Look-aside Buffer (TLB). A TLB-access takes $20$ nanoseconds and the main memory access takes $70$ nanoseconds. If the TLB...
gatecse
603
views
gatecse
asked
Jan 3, 2021
Operating System
go2025-mockgate-1
numerical-answers
translation-lookaside-buffer
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2
votes
2
answers
10
GATE Overflow Test Series | Operating Systems | Test 2 | Question: 22
Consider a paging hardware with a TLB. Assume that the entire page table and all the pages are in the physical memory (no page faults) and there is no cache. It takes $20$ nanoseconds to search the TLB and $300$ ... physical memory. If the TLB hit ratio is $0.9$, the effective memory access time (in nanoseconds) is _________
Consider a paging hardware with a TLB. Assume that the entire page table and all the pages are in the physical memory (no page faults) and there is no cache. It takes $20...
gatecse
201
views
gatecse
asked
Dec 7, 2020
Operating System
go2025-os-2
numerical-answers
memory-management
virtual-memory
translation-lookaside-buffer
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2
votes
2
answers
11
UGC NET CSE | October 2020 | Part 2 | Question: 18
Consider a single-level page table system, with the page table stored in the memory. If the hit rate to TLB is $80\%$, and it takes $15$ nanoseconds to search the $TLB$, and $150$ nanoseconds to access the main memory, then what is the effective memory access time, in nanoseconds? $185$ $195$ $205$ $175$
Consider a single-level page table system, with the page table stored in the memory. If the hit rate to TLB is $80\%$, and it takes $15$ nanoseconds to search the $TLB$, ...
go_editor
2.1k
views
go_editor
asked
Nov 20, 2020
Operating System
ugcnetcse-oct2020-paper2
operating-system
translation-lookaside-buffer
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2
votes
2
answers
12
NIELIT 2017 July Scientist B (CS) - Section B: 32
A CPU generates $32$-bit virtual addresses. The page size is $4$ KB. The processor has a Translation Look-aside Buffer (TLB) which can hold a total of $128$ page table entries and is $4$-way set associative. The minimum size of the TLB tag is $\text{11 bits}$ $\text{13 bits}$ $\text{15 bits}$ $\text{20 bits}$
A CPU generates $32$-bit virtual addresses. The page size is $4$ KB. The processor has a Translation Look-aside Buffer (TLB) which can hold a total of $128$ page table en...
admin
1.2k
views
admin
asked
Mar 30, 2020
Operating System
nielit2017july-scientistb-cs
operating-system
memory-management
paging
translation-lookaside-buffer
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0
votes
0
answers
13
Andrew S. Tanenbaum (OS) Edition 4 Exercise 3 Question 55 (Page No. 261 - 262)
Write a program that can be used to compare the effectiveness of adding a tag field to $TLB$ entries when control is toggled between two programs. The tag field is used to effectively label each entry with the ... for a simple (but nontrivial) input example. Plot the number of $TLB$ updates per $1000$ references.
Write a program that can be used to compare the effectiveness of adding a tag field to $TLB$ entries when control is toggled between two programs. The tag field is used t...
admin
362
views
admin
asked
Oct 26, 2019
Operating System
tanenbaum
operating-system
memory-management
paging
translation-lookaside-buffer
descriptive
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0
votes
0
answers
14
Andrew S. Tanenbaum (OS) Edition 4 Exercise 3 Question 53 (Page No. 261)
Write a program that demonstrates the effect of $TLB$ misses on the effective memory access time by measuring the per-access time it takes to stride through a large array. Explain the main concepts behind the ... but for an older computer with a different architecture and explain any major differences in the output.
Write a program that demonstrates the effect of $TLB$ misses on the effective memory access time by measuring the per-access time it takes to stride through a large array...
admin
431
views
admin
asked
Oct 26, 2019
Operating System
tanenbaum
operating-system
memory-management
virtual-memory
translation-lookaside-buffer
descriptive
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0
votes
0
answers
15
Andrew S. Tanenbaum (OS) Edition 4 Exercise 3 Question 23 (Page No. 256)
How can the associative memory device needed for a $TLB$ be implemented in hardware, and what are the implications of such a design for expandability?
How can the associative memory device needed for a $TLB$ be implemented in hardware, and what are the implications of such a design for expandability?
admin
278
views
admin
asked
Oct 26, 2019
Operating System
tanenbaum
operating-system
memory-management
paging
translation-lookaside-buffer
descriptive
+
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1
votes
1
answer
16
Andrew S. Tanenbaum (OS) Edition 4 Exercise 3 Question 22 (Page No. 256)
A computer whose processes have $1024$ pages in their address spaces keeps its page tables in memory. The overhead required for reading a word from the page table is $5\: nsec.$ To reduce this overhead, the computer has a $TLB,$ ... a lookup in $1\: nsec.$ What hit rate is needed to reduce the mean overhead to $2\: nsec?$
A computer whose processes have $1024$ pages in their address spaces keeps its page tables in memory. The overhead required for reading a word from the page table is $5\:...
admin
780
views
admin
asked
Oct 26, 2019
Operating System
tanenbaum
operating-system
memory-management
paging
translation-lookaside-buffer
descriptive
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1
votes
2
answers
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Andrew S. Tanenbaum (OS) Edition 4 Exercise 3 Question 16 (Page No. 255)
You are given the following data about a virtual memory system: The $TLB$ can hold $1024$ entries and can be accessed in $1$ clock cycle $(1\: nsec).$ A page table entry can be found in $100$ ... $0.01\%$ lead to a page fault, what is the effective address-translation time?
You are given the following data about a virtual memory system:The $TLB$ can hold $1024$ entries and can be accessed in $1$ clock cycle $(1\: nsec).$ A page table entry c...
admin
664
views
admin
asked
Oct 26, 2019
Operating System
tanenbaum
operating-system
memory-management
virtual-memory
translation-lookaside-buffer
descriptive
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1
votes
1
answer
18
Andrew S. Tanenbaum (OS) Edition 4 Exercise 3 Question 11 (Page No. 255)
Consider the following C program: int X[N]; int step = M; /* M is some predefined constant */ for (int i = 0; i < N; i += step) X[i] = X[i] + 1; If this program is run on a machine with ... for every execution of the inner loop? Would your answer in part $(a)$ be different if the loop were repeated many times? Explain.
Consider the following C program: int X[N]; int step = M; /* M is some predefined constant */ for (int i = 0; i < N; i += step) X[i] = X[i] + 1;If this program is run on ...
admin
576
views
admin
asked
Oct 26, 2019
Operating System
tanenbaum
operating-system
memory-management
paging
translation-lookaside-buffer
descriptive
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0
votes
1
answer
19
Self Doubt : Regarding TLB entry for a page not present in memory
If a page is not present in the memory, then its corresponding entry in the page table would have the ‘Present’ bit set as 0 to indicate , the page is not present. Will this entry be considered for caching in TLB? As I understand from above line in Tanenbaum, The entry should not be present in TLB. Is my understanding right?
If a page is not present in the memory, then its corresponding entry in the page table would have the ‘Present’ bit set as 0 to indicate , the page is not present.Wil...
Mayank0343
560
views
Mayank0343
asked
May 8, 2019
Operating System
self-doubt
operating-system
translation-lookaside-buffer
+
–
1
votes
1
answer
20
ISI2017-PCB-CS-5(b)
Consider a paging system with the page table stored in memory. If a memory reference takes $200$ nanoseconds, how long does a paged memory reference take? If we add a Translation Lookaside Buffer (TLB) and $75$ percent of all page-table references are ... memory reference time? Assume that finding a page-table entry in the TLB takes $20$ nanoseconds, if the entry is present.
Consider a paging system with the page table stored in memory. If a memory reference takes $200$ nanoseconds, how long does a paged memory reference take? If we add a Tra...
akash.dinkar12
8.3k
views
akash.dinkar12
asked
Apr 8, 2019
Operating System
isi2017-pcb-cs
operating-system
paging
translation-lookaside-buffer
descriptive
+
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0
votes
1
answer
21
Galvin Edition 9 Exercise 9 Question 15 (Page No. 452)
A simplified view of thread states is $Ready$, $Running$, and $Blocked$,where a thread is either ready and waiting to be scheduled, is running on the processor, or is blocked (for example, waiting for I/O). This is illustrated ... the thread change state if an address reference is resolved in the page table? If so, to what state will it change?
A simplified view of thread states is $Ready$, $Running$, and $Blocked$,where a thread is either ready and waiting to be scheduled, is running on the processor, or is blo...
akash.dinkar12
542
views
akash.dinkar12
asked
Mar 21, 2019
Operating System
galvin
operating-system
virtual-memory
translation-lookaside-buffer
descriptive
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0
votes
1
answer
22
Galvin Edition 9 Exercise 9 Question 14 (Page No. 452)
Assume that a program has just referenced an address in virtual memory. Describe a scenario in which each of the following can occur. (If no such scenario can occur, explain why.) • $TLB$ miss with no page fault • $TLB$ miss and page fault • $TLB$ hit and no page fault • $TLB$ hit and page fault
Assume that a program has just referenced an address in virtual memory. Describe a scenario in which each of the following can occur. (If no such scenario can occur, expl...
akash.dinkar12
2.4k
views
akash.dinkar12
asked
Mar 21, 2019
Operating System
galvin
operating-system
virtual-memory
translation-lookaside-buffer
descriptive
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1
votes
0
answers
23
Caching
Given the following information: TLB hit rate 95%, TLB access time is 1 cycle. cache hit rate 90 %, cache access time is 1 cycle. When TLB and cache both get miss; page fault rate is 1% The TLB access and acache access are ... cycles Access to hard drive requires 50,000 cycles. Compute the average memory access latencies when the cache is physically addresses (in cycles).
Given the following information: • TLB hit rate 95%, TLB access time is 1 cycle. • cache hit rate 90 %, cache access time is 1 cycle. • When TLB and cache both get ...
s_dr_13
1.1k
views
s_dr_13
asked
Mar 10, 2019
CO and Architecture
cache-memory
co-and-architecture
virtual-memory
translation-lookaside-buffer
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–
0
votes
0
answers
24
effective memory access time
A demand paging uses a TLB and a single level page table stored in main memory. The memory access time is 5s. The page fault service time is 25s. If 70% of access is in TLB and of the remaining, 20% is not present in the main memory. The effective memory access time is? Thanks!
A demand paging uses a TLB and a single level page table stored in main memory. The memory access time is 5s. The page fault service time is 25s. If 70% of access is in T...
Abhipsa
1.2k
views
Abhipsa
asked
Jan 27, 2019
Operating System
operating-system
translation-lookaside-buffer
hit-ratio
paging
virtual-memory
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0
votes
0
answers
25
TLB misses
1 2 2048 none
122048none
gate_forum
287
views
gate_forum
asked
Jan 13, 2019
Operating System
operating-system
translation-lookaside-buffer
paging
+
–
2
votes
1
answer
26
TLB hit ration and memory lookup time
Consider a system where TLB lookup time is $25$ ns and memory access time is $200$ ns, respectively. Assuming a virtual address space of $2$ KB, page size of $32$ bytes, and a PTE size of $2$ bytes, what is the minimum TLB hit ratio that results in an average v2p (virtual to physical) translation latency of $185$ ns?
Consider a system where TLB lookup time is $25$ ns and memory access time is $200$ ns, respectively. Assuming a virtual address space of $2$ KB, page size of $32$ bytes, ...
dd
763
views
dd
asked
Jan 13, 2019
Operating System
translation-lookaside-buffer
hit-ratio
+
–
0
votes
1
answer
27
me test series
A computer system implements a 38 bit virtual address, page size of 16 KB, and 256 entries translation look aside buffer (TLB) organized into 32 sets each having 8 ways. If TLB tag does not store any process id. The minimum length of TLB tag in bits is____
A computer system implements a 38 bit virtual address, page size of 16 KB, and 256 entries translation look aside buffer (TLB) organized into 32 sets each having 8 ways. ...
newdreamz a1-z0
506
views
newdreamz a1-z0
asked
Jan 11, 2019
Operating System
translation-lookaside-buffer
operating-system
+
–
0
votes
0
answers
28
UPPCL AE 2018:57
Consider the following $\text{C}$ function executed in an $\text{OS}$ with paging where the page size is $4$ kilobytes. Further, assume that the system employs a $32-$ entry direct mapped $\text{TLB}$ int *alloc_and_init() { int counter, value = 0, size = 2048; int ... of the program, what is the number of $\text{TLB}$ misses during the execution of the for loop? $2048$ $2$ $0$ $1$
Consider the following $\text{C}$ function executed in an $\text{OS}$ with paging where the page size is $4$ kilobytes. Further, assume that the system employs a $32-$ en...
admin
269
views
admin
asked
Jan 5, 2019
Operating System
uppcl2018
operating-system
memory-management
page-fault
translation-lookaside-buffer
+
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