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Questions by Amit Pal
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1
Virtual Gate 2016  Digital Logic Test
asked
Jan 14
in
Digital Logic

66
views
digitallogic
digitalcounter
virtualgate
+1
vote
1
answer
2
Digital Logic
The 4 bit shift register is initialized to value 1000 for (Q3,Q2,Q1,Q0) . The D input is derived from the Q0,Q2,and Q3 through two XOR gates as shown in figure below . The Pattern 0001 will appear at pulse  ? D Q0 Q1 Q2 Q3 and logic gates are XNOR (order in image . I wrote it because in the image it is not clear) .
asked
Nov 4, 2016
in
Digital Logic

79
views
digitallogic
digitalcircuits
combinational
+1
vote
1
answer
3
Digital Logic
Kindly explain this question about shift register.
asked
Nov 4, 2016
in
Digital Logic

78
views
digitallogic
digitalcircuits
+6
votes
2
answers
4
Virtual Gate TOC
Let A be a regular set . Consider the two sets below: L1 = {$x \mid \exists{n}\geq 0 , \exists{y} \in A : y =x^{n}$} L2 = {$x \mid \exists{n}\geq 0 , \exists{y} \in A : x =y^{n}$} Which of the following is True ? L1 and L2 are Regular L1 is Regular but Not L2 L2 is Regular but Not L1 Both are not Regular
asked
Oct 24, 2016
in
Theory of Computation

975
views
theoryofcomputation
virtualgate
testseries
regularlanguages
identifyclasslanguage
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