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Questions by Bikram
0
votes
1
answer
61
Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 30
Consider a hypothetical processor that supports two address, one address and zero address instructions. It has a $256$ word memory, and a $20$ bit instruction is placed in $1$ word of memory (memory ... one address instructions. The total number of zero address instructions formulated is ________ (put in integers only)
Consider a hypothetical processor that supports two address, one address and zero address instructions. It has a $256$ word memory, and a $20$ bit instruction is placed i...
332
views
asked
May 27, 2017
CO and Architecture
tbb-coa-2
numerical-answers
co-and-architecture
instruction-format
+
–
1
votes
1
answer
62
Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 29
Suppose in a system we store data using arrays, we have $2$ arrays A1 and A2. Array A1 contains $256$ elements of size $4$ bytes each. The first element is stored at physical address $4096$ ... of bytes that will be written to memory during execution of the loop is : $256$ $1$ $0$ $2048$
Suppose in a system we store data using arrays, we have $2$ arrays A1 and A2. Array A1 contains $256$ elements of size $4$ bytes each. The first element is stored at phy...
505
views
asked
May 27, 2017
CO and Architecture
tbb-coa-2
co-and-architecture
cache-memory
+
–
0
votes
1
answer
63
Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 28
Consider the following Micro-operations: ... Memory Buffer Register The given micro-operations describes : Interrupt Cycle Fetch Cycle Execute Cycle Indirect Cycle
Consider the following Micro-operations:$\begin{array}{|l|l|} \hline \text{MAR} & \leftarrow IR \text{[address]} \\ \hline \text{MBR} & \leftarrow \text{Memory} \\ \hline...
598
views
asked
May 27, 2017
CO and Architecture
tbb-coa-2
co-and-architecture
microprogramming
+
–
0
votes
2
answers
64
Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 27
Consider a memory hierarchy system consisting of two levels. The access time of level $1$ is $2$ ns. The miss penalty (The time to get data from level $2$, in case of miss) is $100$ ns. If the average memory ... the average access time to $40 \%$, the probability that valid data found in level $1$ is ___________ $\%$
Consider a memory hierarchy system consisting of two levels. The access time of level $1$ is $2$ ns. The miss penalty (The time to get data from level $2$, in case of mis...
366
views
asked
May 27, 2017
CO and Architecture
tbb-coa-2
numerical-answers
co-and-architecture
cache-memory
+
–
0
votes
1
answer
65
Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 26
Which of the following statements is/are correct about hazards? One way to implement branch prediction is to store the result of a branch condition in a branch target buffer to help guide instruction pre-fetching if the branch is ... whether the branch is taken. III only II and III only I and III only I, II, and III
Which of the following statements is/are correct about hazards?One way to implement branch prediction is to store the result of a branch condition in a branch target buff...
259
views
asked
May 27, 2017
CO and Architecture
tbb-coa-2
co-and-architecture
pipelining
data-dependency
+
–
2
votes
2
answers
66
Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 25
Suppose there are $500$ memory references in which $50$ misses in the $1$st level cache and $20$ misses in the $2$nd level cache . Let the miss penalty from L2 cache to memory is $100$ cycles. ... cycles. If there are $2.5$ memory reference/instruction , average number of stall cycles per instruction will be __________
Suppose there are $500$ memory references in which $50$ misses in the $1$st level cache and $20$ misses in the $2$nd level cache . Let the miss penalty from L2 cache to m...
543
views
asked
May 27, 2017
CO and Architecture
tbb-coa-2
numerical-answers
co-and-architecture
cache-memory
+
–
3
votes
1
answer
67
Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 24
A byte addressable computer can support maximum of $2^i$ KB memory and has $2^j$ instructions. An instruction involving $2$ operands and $1$ operator needs how many bits ? $3i$ $2i + j$ $2i + j + 20$ $i + j$
A byte addressable computer can support maximum of $2^i$ KB memory and has $2^j$ instructions. An instruction involving $2$ operands and $1$ operator needs how many bits ...
273
views
asked
May 27, 2017
CO and Architecture
tbb-coa-2
co-and-architecture
memory-management
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–
0
votes
2
answers
68
Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 23
Consider a two level memory hierarchy having only one level cache and main memory. Cache and Main memory access times are $20$ ns and $120$ ns/word respectively. The size of cache block is $4$ words . If main memory is referenced $40 \%$ of the times, then average access time is _______ ns
Consider a two level memory hierarchy having only one level cache and main memory. Cache and Main memory access times are $20$ ns and $120$ ns/word respectively. The size...
499
views
asked
May 27, 2017
CO and Architecture
tbb-coa-2
numerical-answers
co-and-architecture
cache-memory
+
–
1
votes
1
answer
69
Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 22
Suppose that a direct-mapped cache has $2^{10}$ cache lines, with $2^4$ bytes of data per cache line. If the cache is used to store blocks for a byte addressable memory of size $2^{30}$ bytes, then number of bytes of space will be required for storing the tags is ________ (put the integer value)
Suppose that a direct-mapped cache has $2^{10}$ cache lines, with $2^4$ bytes of data per cache line. If the cache is used to store blocks for a byte addressable memory ...
270
views
asked
May 27, 2017
CO and Architecture
tbb-coa-2
numerical-answers
co-and-architecture
cache-memory
+
–
0
votes
2
answers
70
Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 21
Consider a $5$ stage instruction pipeline which can implement the $4$ instructions $I1, \ I2, \ I3, \ I4$ ... The speed up of the pipeline is approximately ________
Consider a $5$ stage instruction pipeline which can implement the $4$ instructions $I1, \ I2, \ I3, \ I4$. Below table gives the number of clocks required per instruction...
357
views
asked
May 27, 2017
CO and Architecture
tbb-coa-2
numerical-answers
co-and-architecture
pipelining
+
–
2
votes
2
answers
71
Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 20
Suppose there are $m$ instructions to be executed in a program. $p$ is the probability that an instruction is a conditional branch instruction, and $q$ is the probability of a successful branch. Assume the average number of instructions completed in a simple ... $pq (mn -1) + p( 1- q) mn$ $1 +pq ( n - 1)$ $p - pq$
Suppose there are $m$ instructions to be executed in a program. $p$ is the probability that an instruction is a conditional branch instruction, and $q$ is the probabilit...
524
views
asked
May 27, 2017
CO and Architecture
tbb-coa-2
pipelining
co-and-architecture
+
–
1
votes
1
answer
72
Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 19
Consider the following two types of Cache Designs : Cache $1$: It is a direct-mapped cache with eight $1$ - word cache lines. The miss penalty is $8$ clock cycles. Cache $2$ : It is a two-way associative cache with ... cycles and Cache $2$ spends $60$ cycles Cache $1$ spends $56$ cycles and Cache $2$ spends $70$ cycles
Consider the following two types of Cache Designs : Cache $1$: It is a direct-mapped cache with eight $1$ – word cache lines. The miss penalty is $8$ clock cycles.Cache...
299
views
asked
May 27, 2017
CO and Architecture
tbb-coa-2
co-and-architecture
pipelining
+
–
0
votes
1
answer
73
Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 18
Match the pairs about implementation and addressing modes: ... (A-III), (B-I), (C-II) (A-III), (B-II), (C-I) (A-II), (B-III), (C-I)
Match the pairs about implementation and addressing modes:$\begin{array}{|l|l|l|l|} \hline {} & \text{Group A} & {} & \text{Group B} \\ \hline A. & \text{Array} & I. & \t...
188
views
asked
May 27, 2017
CO and Architecture
tbb-coa-2
co-and-architecture
addressing-modes
+
–
1
votes
1
answer
74
Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 17
Consider a pipelined system with these $4$ phases: FI - Fetch instruction DA - Decode and calculate address FO - Fetch Operand EX- Execute instruction Each phase requires one clock cycle. There were four ... exists pipeline hazards , then the number of clock cycles required to complete the above program is _________
Consider a pipelined system with these $4$ phases:FI – Fetch instructionDA – Decode and calculate addressFO – Fetch OperandEX- Execute instructionEach phase requi...
507
views
asked
May 27, 2017
CO and Architecture
tbb-coa-2
numerical-answers
co-and-architecture
pipelining
+
–
0
votes
1
answer
75
Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 16
Consider the following statements about the Locality of Reference principle used in the computer memory systems. The principal states that an already accessed memory location is accessed further again and it is also more likely that ... the above statements is/are TRUE? I only II only II and III only I and III only
Consider the following statements about the Locality of Reference principle used in the computer memory systems.The principal states that an already accessed memory locat...
252
views
asked
May 27, 2017
CO and Architecture
tbb-coa-2
co-and-architecture
cache-memory
+
–
0
votes
4
answers
76
Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 15
Consider a $2$ - way set associative cache memory with $4$ sets and total $8$ cache blocks $(0 - 7)$. Main memory has $64$ blocks $(0 - 63)$. If LRU policy is used for replacement and cache is initially empty then total number of conflict cache ... block references is: $0 \ 5 \ 9 \ 13 \ 7 \ 0 \ 15 \ 25$ $2$ $3$ $0$ $1$
Consider a $2$ – way set associative cache memory with $4$ sets and total $8$ cache blocks $(0 – 7)$. Main memory has $64$ blocks $(0 - 63)$. If LRU policy is used fo...
815
views
asked
May 27, 2017
CO and Architecture
tbb-coa-2
co-and-architecture
cache-memory
conflict-misses
+
–
0
votes
0
answers
77
Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 14
Match the following: ... -s i-r, ii-s, iii-q, iv-p i-r, ii-s, iii-p, iv-q i-r, ii-p, iii-s, iv-q
Match the following:$\begin{array}{|l|l|l|l|} \hline (i) & \text{Base addressing} & (p) & \text{Pointers} \\ \hline (ii) & \text{Indexed addressing} & (q) & \text{Loops} ...
270
views
asked
May 27, 2017
CO and Architecture
tbb-coa-2
computer-architecture
addressing-modes
match-the-following
+
–
0
votes
1
answer
78
Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 13
What is the total number of Read after Write (RAW), Write after Read (WAR) and Write after Write (WAW) dependencies, respectively in the following assembly program? ... $2,1,3$ $3,1,2$ $1,2,3$ $3,2,1$
What is the total number of Read after Write (RAW), Write after Read (WAR) and Write after Write (WAW) dependencies, respectively in the following assembly program?$\begi...
279
views
asked
May 27, 2017
CO and Architecture
tbb-coa-2
pipelining
co-and-architecture
data-hazards
+
–
0
votes
1
answer
79
Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 12
A $4$ way set associative cache with a size of $32$ KB has line size $16$ Bytes. There is a Byte addressable main memory with a size of $256$ MB, then which of the following Main Memory block is mapped on to the set $'0'$ of Cache Memory? $(FCEE90B)16$ $(FECF10C)16$ $(CFEE09B)16$ $(CDDE00B)16$
A $4$ way set associative cache with a size of $32$ KB has line size $16$ Bytes. There is a Byte addressable main memory with a size of $256$ MB, then which of the follow...
301
views
asked
May 27, 2017
CO and Architecture
tbb-coa-2
co-and-architecture
cache-memory
+
–
0
votes
1
answer
80
Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 11
A control unit has control signals which can be divided into $5$ mutually exclusive groups of $30, 70, 12, 25$ and $23$ control signals respectively. The number of bits that are saved using vertical micro-programming over horizontal programming is ___________
A control unit has control signals which can be divided into $5$ mutually exclusive groups of $30, 70, 12, 25$ and $23$ control signals respectively. The number of bits t...
252
views
asked
May 27, 2017
CO and Architecture
tbb-coa-2
numerical-answers
co-and-architecture
microprogramming
horizontal-microprogramming
+
–
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