0 votes
1 answer
63
Consider the following Micro-operations:$\begin{array}{|l|l|} \hline \text{MAR} & \leftarrow IR \text{[address]} \\ \hline \text{MBR} & \leftarrow \text{Memory} \\ \hline...
3 votes
1 answer
67
0 votes
2 answers
70
Consider a $5$ stage instruction pipeline which can implement the $4$ instructions $I1, \ I2, \ I3, \ I4$. Below table gives the number of clocks required per instruction...
0 votes
1 answer
73
Match the pairs about implementation and addressing modes:$\begin{array}{|l|l|l|l|} \hline {} & \text{Group A} & {} & \text{Group B} \\ \hline A. & \text{Array} & I. & \t...
0 votes
0 answers
77
Match the following:$\begin{array}{|l|l|l|l|} \hline (i) & \text{Base addressing} & (p) & \text{Pointers} \\ \hline (ii) & \text{Indexed addressing} & (q) & \text{Loops} ...
0 votes
1 answer
78