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Questions by SeemaTanwar
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Doubt -OS process scheduling
If arrival time of a process is same as the end time of quantum slice for a process in round robin schedule then in what order we must place the processes in ready queue?
If arrival time of a process is same as the end time of quantum slice for a process in round robin schedule then in what order we must place the processes in ready queue?...
497
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asked
Dec 20, 2018
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2
avl tree-AAI exam
302
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asked
Dec 11, 2018
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answer
3
Leaky Bucket
706
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asked
Nov 26, 2018
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4
Made Easy test series
244
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asked
Oct 5, 2018
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5
clock cycles to access ALU and Register in Base Index addressing mOde
How many cycles will be required to fetch an operand if we are using "BASE INDEX' addressing mode, and ALU computation takes 2 cycles, register reference takes 1 cycle and memory reference takes 4 cycles each respectively ?
How many cycles will be required to fetch an operand if we are using "BASE INDEX' addressing mode, and ALU computation takes 2 cycles, register reference takes 1 cycle an...
482
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asked
Jan 28, 2018
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6
shift register
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Jan 6, 2018
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7
cache memory
A 2-way set associative write back cache with true LRU replacement requires 15 * 29 bits to implement its tag store per set (including bits for valid, dirty and LRU). The cache is virtually indexed, physically tagged. The virtual address space is 1 MB, page size ... , cache block size is 8 bytes and is byte addressable. What is the maximum size of the data store of the cache in bytes?
A 2-way set associative write back cache with true LRU replacement requires 15 * 29 bits to implement its tag store per set(including bits for valid, dirty and LRU). The ...
187
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asked
Dec 26, 2017
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cache hit latency computation
Consider 32 KB 4-way set associative cache with 32 byte block size. CPU generates 32 bits physical address . A 4 to1 multiplexer has a latency of 1 ns while a k bit comparator has a latency of 2k ns. The hit latency of the cache organization is?
Consider 32 KB 4-way set associative cache with 32 byte block size. CPU generates 32 bits physical address . A 4 to1multiplexer has a latency of 1 ns while a k bit compar...
424
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asked
Dec 26, 2017
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9
memory access time
Consider a computer system in which cache memory write hit takes 10 ns and and miss takes 100 ns. Cache memory read hit takes 5ns and miss takes 55 ns. The cache is having 90% hit. The system received 1000 fetch instructions out of which, 500 operand fetch operations and 500 operand write operations. The average time taken to execute above 1000 instructions is_
Consider a computer system in which cache memory write hit takes 10 ns and and miss takes 100 ns. Cache memory read hittakes 5ns and miss takes 55 ns. The cache is having...
293
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asked
Dec 25, 2017
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hit ratio computation
Consider a 4-way set associative cache that has 8 lines,with perfect LRU cache replacement and supports a block size of 16 bytes. For the following memory access pattern (shown as byte addresses), find the hit ratio? 3, 5, 6, 21, 32, 14, 5, 10, 11, 12 ?
Consider a 4-way set associative cache that has 8 lines,with perfect LRU cache replacement and supports a block size of16 bytes.For the following memory access pattern (s...
314
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asked
Dec 25, 2017
1
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pre-emptive scheduling
22. Given the jobs with the following characteristics: job A: 5ms CPU , 25 ms IO , 5 ms CPU job B: 20ms CPU, 15 ms IO job C: 40 ms cpu Determine the turnaround time, waiting time and response time of Job B while the CPU runs these jobs. Assume the schedule is preemptive and the CPU quantum is 5 ms
22. Given the jobs with the following characteristics:job A: 5ms CPU , 25 ms IO , 5 ms CPUjob B: 20ms CPU, 15 ms IOjob C: 40 ms cpuDetermine the turnaround time, waiting ...
247
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asked
Dec 24, 2017
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Round Robin scheduling policy
The I/O wait percentage p of a process is the percentage of time the process wait for an IO to completion when executed in a monoprogramming environment . on a system using round robin with n process ,all having same IO . what percentage of time cpu will be idle in term of (p) ?
The I/O wait percentage p of a process is the percentage of time theprocess wait for an IO to completion when executed in amonoprogramming environment . on a system using...
243
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asked
Dec 24, 2017
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13
Ace test series question on scheduling policy
which scheduling policy is starvation free? A) LIFO B) FIFO C) SJF D)PRIORITY
which scheduling policy is starvation free?A) LIFOB) FIFOC) SJFD)PRIORITY
579
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asked
Dec 23, 2017
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EKT-423: OPERATING SYSTEM TUTORIAL 01
4. A computer has a cache, main memory, and a disk used for virtual memory. If a referenced word is in the cache, 20 ns are required to access it. If it is in main memory but not in the cache, 60 ns are needed to load it ... main-memory hit ratio is 0.6 (60%) . What is the average time in ns required to access a referenced word on this system?
4. A computer has a cache, main memory, and a diskused for virtual memory. If a referenced wordis in the cache, 20 nsare required to access it. If it is in main memory bu...
432
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asked
Dec 22, 2017
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15
Test series question............
In a 6 bit ripple counter the MOD of up counting is 14, then MOD of down counting is?
In a 6 bit ripple counter the MOD of up counting is 14, then MOD of down counting is?
362
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asked
Dec 20, 2017
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MP481 Review Problems Turing Machines and (Un)Decidability Luay K. Nakhleh
L1={<M>|M is a TM and |L(M)|<=3} L2={<M>|M is a TM and |L(M)|>=3} L3={<M>|M is a TM and L(M) is finite} How can we judge which language is rec, R. E or not R. E?
L1={<M>|M is a TM and |L(M)|<=3}L2={<M>|M is a TM and |L(M)|>=3}L3={<M>|M is a TM and L(M) is finite}How can we judge which language is rec, R. E or not R. E?
267
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asked
Dec 27, 2016
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