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1
answer
1
ISRO2014-30
Every time the attribute A appears, it is matched with the same value of attribute B but not the same value of attribute C. Which of the following is true? A -> (B,C) A -> B, A ->> C A -> B, C ->> A A ->> B, B -> C
Every time the attribute A appears, it is matched with the same value of attribute B but not the same value of attribute C. Which of the following is true?A - (B,C) ...
6.7k
views
comment edited
Jul 4, 2016
Databases
databases
database-normalization
isro2014
+
–
2
answers
2
ISRO2016-17
Which of the following binary number is the same as its $2's$ complement ? $1010$ $0101$ $1000$ $1001$
Which of the following binary number is the same as its $2's$ complement ?$1010$$0101$$1000$$1001$
11.5k
views
commented
Jul 3, 2016
Digital Logic
digital-logic
number-representation
isro2016
+
–
10
answers
3
ISRO2015-38
Suppose two jobs, each of which needs $10$ minutes of CPU time, start simultaneously. Assume $50\%$ I/O wait time. How long will it take for both to complete, if they run sequentially? 10 20 30 40
Suppose two jobs, each of which needs $10$ minutes of CPU time, start simultaneously. Assume $50\%$ I/O wait time. How long will it take for both to complete, if they run...
11.2k
views
commented
Jun 30, 2016
Operating System
process-scheduling
isro2015
+
–
3
answers
4
GATE CSE 1994 | Question: 21
Consider the following recursive function: function fib (n:integer);integer; begin if (n=0) or (n=1) then fib := 1 else fib := fib(n-1) + fib(n-2) end; The above function is run on a computer with a stack of $64$ bytes. Assuming ... an address takes $2$ bytes each, estimate the maximum value of $n$ for which the stack will not overflow. Give reasons for your answer.
Consider the following recursive function:function fib (n:integer);integer; begin if (n=0) or (n=1) then fib := 1 else fib := fib(n-1) + fib(n-2) end;The above function i...
25.5k
views
commented
Jun 28, 2016
Programming in C
gate1994
programming
recursion
normal
descriptive
+
–
9
answers
5
GATE CSE 2016 Set 1 | Question: 38
Consider the weighted undirected graph with $4$ vertices, where the weight of edge $\{i,j\}$ is given by the entry $W_{ij}$ in the matrix $W$ ... integer value of $x$, for which at least one shortest path between some pair of vertices will contain the edge with weight $x$ is ___________.
Consider the weighted undirected graph with $4$ vertices, where the weight of edge $\{i,j\}$ is given by the entry $W_{ij}$ in the matrix $W$. W=$\begin{bmatrix} 0&2 &8 &...
24.0k
views
comment edited
Jun 21, 2016
DS
gatecse-2016-set1
data-structures
graph-theory
normal
numerical-answers
+
–
4
answers
6
GATE CSE 2016 Set 1 | Question: 37
An operator $delete(i)$ for a binary heap data structure is to be designed to delete the item in the $i$-th node. Assume that the heap is implemented in an array and $i$ refers to the $i$-th index of the array. If the heap tree has depth $d$ (number of edges on the path from the root ... $O(d)$ but not $O(1)$ $O(2^d)$ but not $O(d)$ $O(d \ 2^d)$ but not $O(2^d)$
An operator $delete(i)$ for a binary heap data structure is to be designed to delete the item in the $i$-th node. Assume that the heap is implemented in an array and $i$...
15.3k
views
answered
Jun 21, 2016
DS
gatecse-2016-set1
data-structures
binary-heap
normal
+
–
2
answers
7
ISRO2008-4
On a LAN ,where are IP datagrams transported? In the LAN header In the application field In the information field of the LAN frame After the TCP header
On a LAN ,where are IP datagrams transported?In the LAN headerIn the application fieldIn the information field of the LAN frameAfter the TCP header
5.1k
views
comment edited
Jun 12, 2016
Computer Networks
isro2008
computer-networks
lan-technologies
+
–
4
answers
8
GATE CSE 2016 Set 2 | Question: 32
The width of the physical address on a machine is $40$ bits. The width of the tag field in a $512$ KB $8$-way set associative cache is ________ bits.
The width of the physical address on a machine is $40$ bits. The width of the tag field in a $512$ KB $8$-way set associative cache is ________ bits.
17.8k
views
answered
Apr 5, 2016
CO and Architecture
gatecse-2016-set2
co-and-architecture
cache-memory
normal
numerical-answers
+
–
7
answers
9
GATE CSE 2016 Set 2 | Question: 35
The following function computes $X^{Y}$ for positive integers $X$ and $Y$. int exp (int X, int Y) { int res =1, a = X, b = Y; while (b != 0) { if (b % 2 == 0) {a = a * a; b = b/2; } else {res = res * a; b = b - 1; } } return res; } Which one of the following ... $X^{Y} = a^{b}$ $(res * a)^{Y} = (res * X)^{b}$ $X^{Y} = res * a^{b}$ $X^{Y} = (res * a)^{b}$
The following function computes $X^{Y}$ for positive integers $X$ and $Y$.int exp (int X, int Y) { int res =1, a = X, b = Y; while (b != 0) { if (b % 2 == 0) {a =...
14.0k
views
answered
Feb 13, 2016
Programming in C
gatecse-2016-set2
programming
loop-invariants
normal
+
–
8
answers
10
GATE CSE 2016 Set 2 | Question: 33
Consider a $3 \ \text{GHz}$ (gigahertz) processor with a three stage pipeline and stage latencies $\large\tau_1,\tau_2$ and $\large\tau_3$ such that $\large\tau_1 =\dfrac{3 \tau_2}{4}=2\tau_3$. If the longest pipeline stage is split into two pipeline stages of equal latency , the new frequency is __________ $\text{GHz}$, ignoring delays in the pipeline registers.
Consider a $3 \ \text{GHz}$ (gigahertz) processor with a three stage pipeline and stage latencies $\large\tau_1,\tau_2$ and $\large\tau_3$ such that $\large\tau_1 =\dfrac...
19.2k
views
answered
Feb 13, 2016
CO and Architecture
gatecse-2016-set2
co-and-architecture
pipelining
normal
numerical-answers
+
–
3
answers
11
GATE CSE 2010 | Question: 33
A $5-$stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take $1$ clock cycle each for any instruction. The PO stage takes $1$ clock cycle for ... $13$ $15$ $17$ $19$
A $5-$stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID,...
22.1k
views
commented
Nov 25, 2015
CO and Architecture
gatecse-2010
co-and-architecture
pipelining
normal
+
–
4
answers
12
Why is the maximum number of tuples in full outer join equal to m*n ?
Why is the maximum number of tuples in full outer join equal to m*n, where m is the number of attributes in one relation and n is the attribute count in other ? Can someone give an example to illustrate this ?
Why is the maximum number of tuples in full outer join equal to m*n, where m is the number of attributes in one relation and n is the attribute count in other ?Can someon...
3.4k
views
commented
Oct 22, 2015
Databases
databases
relational-algebra
+
–
5
answers
13
ISRO2015-53
An ACK number of $1000$ in TCP always means that $999$ bytes have been successfully received $1000$ bytes have been successfully received $1001$ bytes have been successfully received None of the above
An ACK number of $1000$ in TCP always means that$999$ bytes have been successfully received$1000$ bytes have been successfully received$1001$ bytes have been successfully...
8.3k
views
asked
Oct 15, 2015
Computer Networks
isro2015
computer-networks
tcp
+
–
2
answers
14
ISRO2015-46
The correct syntax to write "Hi there" in Javascript is jscript.write ("Hi There") response.write ("Hi There") print ("Hi There") print.jscript ("Hi There")
The correct syntax to write "Hi there" in Javascript isjscript.write ("Hi There")response.write ("Hi There")print ("Hi There")print.jscript ("Hi There")
3.5k
views
asked
Oct 15, 2015
Web Technologies
javascript
non-gate
isro2015
+
–
11
answers
15
ISRO2015-30
Semaphores are used to solve the problem of Race Condition Process Synchronization Mutual Exclusion None of the above I and II II and III All of the above None of the above
Semaphores are used to solve the problem ofRace ConditionProcess SynchronizationMutual ExclusionNone of the aboveI and IIII and IIIAll of the aboveNone of the above
21.6k
views
commented
Oct 13, 2015
Operating System
semaphore
isro2015
process-synchronization
+
–
3
answers
16
ISRO2015-4
A modulus -$12$ ring counter requires a minimum of $10$ flip-flops $12$ flip-flops $8$ flip-flops $6$ flip-flops
A modulus -$12$ ring counter requires a minimum of$10$ flip-flops$12$ flip-flops$8$ flip-flops$6$ flip-flops
10.4k
views
asked
Oct 12, 2015
Digital Logic
isro2015
digital-logic
digital-counter
+
–
5
answers
17
ISRO2015-7
If half adders and full adders are implements using gates, then for the addition of two $17$ bit numbers (using minimum gates) the number of half adders and full adders required will be $0,17$ $16,1$ $1,16$ $8,8$
If half adders and full adders are implements using gates, then for the addition of two $17$ bit numbers (using minimum gates) the number of half adders and full adders r...
9.7k
views
asked
Oct 12, 2015
Digital Logic
isro2015
digital-logic
adder
+
–
5
answers
18
ISRO2015-55
A certain population of ALOHA users manages to generate $70$ request/sec. If the time is slotted in units of $50$ msec, then channel load would be $4.25$ $3.5$ $450$ $350$
A certain population of ALOHA users manages to generate $70$ request/sec. If the time is slotted in units of $50$ msec, then channel load would be$4.25$$3.5$$450$$350$
7.0k
views
asked
Oct 12, 2015
Computer Networks
isro2015
computer-networks
slotted-aloha
+
–
3
answers
19
ISRO2015-62
The minimum time delay between the initiation of two independent memory operations is called Access time Cycle time Rotational time Latency time
The minimum time delay between the initiation of two independent memory operations is calledAccess timeCycle timeRotational timeLatency time
6.8k
views
asked
Oct 12, 2015
CO and Architecture
isro2015
co-and-architecture
memory-management
+
–
5
answers
20
ISRO2015-68
Consider the following program fragment if(a > b) if(b > c) s1; else s2; s2 will be executed if a <= b b > c b >= c and a <= b a > b and b <= c
Consider the following program fragment if(a b) if(b c) s1; else s2;s2 will be executed ifa <= bb cb >= c and a <= ba b and b <= c
5.8k
views
asked
Oct 12, 2015
Programming in C
isro2015
programming
programming-in-c
+
–
3
answers
21
ISRO2015-72
Consider the following declaration: int a, *b=&a, **c=&b; The following program fragment a=4; **c=5; does not change the value of a assigns address of $c$ to $a$ assigns the value of $b$ to $a$ assigns $5$ to $a$
Consider the following declaration:int a, *b=&a, c=&b;The following program fragmenta=4; c=5;does not change the value of aassigns address of $c$ to $a$assigns the valu...
4.7k
views
asked
Oct 12, 2015
Programming in C
pointers
programming-in-c
isro2015
+
–
3
answers
22
ISRO2015-18
Given a block can hold either $3$ records or $10$ key pointers. A database contains n records, then how many blocks do we need to hold the data file and the dense index $13n/30$ $n/3$ $n/10$ $n/30$
Given a block can hold either $3$ records or $10$ key pointers. A database contains n records, then how many blocks do we need to hold the data file and the dense index$1...
7.5k
views
asked
Oct 12, 2015
Databases
isro2015
databases
indexing
+
–
4
answers
23
ISRO2009-69
The 'command' used to change contents of one database using the contents of another database by linking them on a common key field? Replace Join Change Update
The 'command' used to change contents of one database using the contents of another database by linking them on a common key field?ReplaceJoinChangeUpdate
4.6k
views
asked
Oct 5, 2015
Databases
isro2009
databases
bad-question
+
–
4
answers
24
ISRO2009-77
When a process is rolled back as a result of deadlock the difficulty which arises is Starvation System throughput Low device utilization Cycle stealing
When a process is rolled back as a result of deadlock the difficulty which arises isStarvationSystem throughputLow device utilizationCycle stealing
7.2k
views
asked
Oct 5, 2015
Operating System
isro2009
deadlock-prevention-avoidance-detection
+
–
3
answers
25
ISRO2009-78
On receiving an interrupt from an I/O device,the CPU Halts for a predetermined time Branches off to the interrupt service routine after completion of the current instruction Branches off to the interrupt service routine immediately Hands over control of address bus and data bus to the interrupting device
On receiving an interrupt from an I/O device,the CPUHalts for a predetermined timeBranches off to the interrupt service routine after completion of the current instructio...
7.0k
views
asked
Oct 5, 2015
CO and Architecture
isro2009
co-and-architecture
io-handling
+
–
4
answers
26
ISRO2009-79
Compared to CISC processors,RISC processors contain More register and smaller instruction set larger instruction set less registers and smaller instruction set more transistor elements
Compared to CISC processors,RISC processors containMore register and smaller instruction setlarger instruction setless registers and smaller instruction setmore transisto...
4.0k
views
asked
Oct 5, 2015
CO and Architecture
isro2009
co-and-architecture
instruction-format
+
–
1
answer
27
The process of organizing the memory into two banks to allow 8 and 16 bit data operation is called
The process of organizing the memory into two banks to allow 8 and 16 bit data operation is called a)Bank switching b)Indexed mapping c)Two-way memory interleaving d)Memory segmentation
The process of organizing the memory into two banks to allow 8 and 16 bit data operation is calleda)Bank switchingb)Indexed mappingc)Two-way memory interleavingd)Memory s...
1.3k
views
asked
Oct 5, 2015
1
answer
28
Which is the correct definition of a valid process transition in an operating system?
Which is the correct definition of a valid process transition in an operating system? a)Wake up:ready->running b)Dispatch:ready->running c)Block:ready->running d)Timer runout:ready->blocked
Which is the correct definition of a valid process transition in an operating system?a)Wake up:ready->runningb)Dispatch:ready->runningc)Block:ready->runningd)Timer runout...
3.1k
views
asked
Oct 5, 2015
2
answers
29
ISRO2011-69
Lightweight Directory Access protocol is used for Routing the packets Authentication obtaining IP address domain name resolving
Lightweight Directory Access protocol is used forRouting the packetsAuthenticationobtaining IP addressdomain name resolving
2.6k
views
asked
Oct 1, 2015
Computer Networks
isro2011
computer-networks
network-protocols
+
–
2
answers
30
ISRO2011-70
Number of comparisons required for an unsuccessful search of an element in a sequential search organized, fixed length, symbol table of length L is L L/2 (L+1)/2 2L
Number of comparisons required for an unsuccessful search of an element in a sequential search organized, fixed length, symbol table of length L isLL/2(L+1)/22L
6.9k
views
asked
Oct 1, 2015
Algorithms
isro2011
algorithms
searching
+
–
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