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jatinmittal199510
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Recent activity by jatinmittal199510
7
answers
1
GATE IT 2006 | Question: 67
A link of capacity $100$ $\text{Mbps}$ is carrying traffic from a number of sources. Each source generates an on-off traffic stream; when the source is on, the rate of traffic is $10$ $\text{Mbps}$, and when the source is off, the rate of traffic is zero. The duty cycle, which ... $\text{and}$ $30$ $12$ $\text{and}$ $25$ $5$ $\text{and}$ $33$ $15$ $\text{and}$ $22$
A link of capacity $100$ $\text{Mbps}$ is carrying traffic from a number of sources. Each source generates an on-off traffic stream; when the source is on, the rate of tr...
11.1k
views
comment edited
Apr 29, 2021
Computer Networks
gateit-2006
computer-networks
network-flow
normal
+
–
6
answers
2
GATE IT 2004 | Question: 87
A TCP message consisting of $2100$ $bytes$ is passed to IP for delivery across two networks. The first network can carry a maximum payload of $1200$ $bytes$ per frame and the second network can carry a maximum payload of $400$ $bytes$ per frame, excluding ... second network for this transmission? $\text{40 bytes}$ $\text{80 bytes}$ $\text{120 bytes}$ $\text{160 bytes}$
A TCP message consisting of $2100$ $bytes$ is passed to IP for delivery across two networks. The first network can carry a maximum payload of $1200$ $bytes$ per frame an...
19.1k
views
commented
Apr 27, 2021
Computer Networks
gateit-2004
computer-networks
network-flow
normal
+
–
6
answers
3
GATE CSE 2019 | Question: 49
Consider that $15$ machines need to be connected in a LAN using $8$-port Ethernet switches. Assume that these switches do not have any separate uplink ports. The minimum number of switches needed is ______
Consider that $15$ machines need to be connected in a LAN using $8$-port Ethernet switches. Assume that these switches do not have any separate uplink ports. The minimum ...
19.7k
views
commented
Apr 27, 2021
Computer Networks
gatecse-2019
numerical-answers
computer-networks
lan-technologies
2-marks
+
–
5
answers
4
GATE CSE 1995 | Question: 1.12
What is the distance of the following code $000000$, $010101$, $000111$, $011001$, $111111$? $2$ $3$ $4$ $1$
What is the distance of the following code $000000$, $010101$, $000111$, $011001$, $111111$?$2$$3$$4$$1$
7.5k
views
commented
Apr 26, 2021
Computer Networks
gate1995
computer-networks
error-detection
normal
+
–
8
answers
5
GATE CSE 2012 | Question: 44
Consider a source computer $(S)$ transmitting a file of size $10^{6}$ bits to a destination computer $(D)$ over a network of two routers $(R_{1}\text{ and }R_{2})$ and three links $(L_{1},L_{2},\text{ and } L_{3})$. $L_{1}$ connects $S$ to ... propagation delays in transmitting the file from $S$ to $D$? $\text{1005 ms}$ $\text{1010 ms}$ $\text{3000 ms}$ $\text{3003 ms}$
Consider a source computer $(S)$ transmitting a file of size $10^{6}$ bits to a destination computer $(D)$ over a network of two routers $(R_{1}\text{ and }R_{2})$ and th...
25.3k
views
commented
Apr 25, 2021
Computer Networks
gatecse-2012
computer-networks
communication
normal
+
–
7
answers
6
GATE CSE 2014 Set 1 | Question: 55
Consider two processors $P_1$ and $P_2$ executing the same instruction set. Assume that under identical conditions, for the same input, a program running on $P_2$ takes $\text{25%}$ less time but incurs $\text{20%}$ more CPI (clock cycles per instruction) ... If the clock frequency of $P_1$ is $\text{1GHZ}$, then the clock frequency of $P_2$ (in GHz) is ______.
Consider two processors $P_1$ and $P_2$ executing the same instruction set. Assume that under identical conditions, for the same input, a program running on $P_2$ takes $...
17.9k
views
commented
Apr 21, 2021
CO and Architecture
gatecse-2014-set1
co-and-architecture
numerical-answers
normal
speedup
+
–
2
answers
7
GATE CSE 2011 | Question: 41
Consider an instruction pipeline with four stages $\text{(S1, S2, S3 and S4)}$ each with combinational circuit only. The pipeline registers are required between each stage and at the end of the last stage. Delays for the stages and for the pipeline ... under ideal conditions when compared to the corresponding non-pipeline implementation? $4.0$ $2.5$ $1.1$ $3.0$
Consider an instruction pipeline with four stages $\text{(S1, S2, S3 and S4)}$ each with combinational circuit only. The pipeline registers are required between each stag...
13.5k
views
commented
Apr 21, 2021
CO and Architecture
gatecse-2011
co-and-architecture
pipelining
normal
+
–
2
answers
8
GATE IT 2005 | Question: 49
An instruction set of a processor has $125$ signals which can be divided into $5$ groups of mutually exclusive signals as follows: Group $1$ $:$ $20$ signals, Group $2$ $:$ $70$ signals, Group $3$ $:$ $2$ signals, Group $4$ ... signals. How many bits of the control words can be saved by using vertical microprogramming over horizontal microprogramming? $0$ $103$ $22$ $55$
An instruction set of a processor has $125$ signals which can be divided into $5$ groups of mutually exclusive signals as follows:Group $1$ $:$ $20$ signals, Group $2$ $:...
9.2k
views
commented
Apr 20, 2021
CO and Architecture
gateit-2005
co-and-architecture
microprogramming
normal
+
–
7
answers
9
GATE CSE 2007 | Question: 54
In a simplified computer the instructions are: ... computation should be in memory. What is the minimum number of MOV instructions in the code generated for this basic block? $2$ $3$ $5$ $6$
In a simplified computer the instructions are:$$\begin{array}{|l|l|} \hline \text {OP }R _j , R _i & \text{Perform }R _j \text{ OP } R _i \text{ and store the result in r...
13.4k
views
commented
Apr 20, 2021
CO and Architecture
gatecse-2007
co-and-architecture
machine-instruction
normal
+
–
3
answers
10
GATE CSE 1999 | Question: 17
Consider the following program fragment in the assembly language of a certain hypothetical processor. The processor has three general purpose registers $R1, R2$and $R3$. The meanings of the instructions are shown by comments (starting with ;) after the instructions. ... the values n, 0, and 0 respectively. What is the final value of $R3$ when control reaches $Z$?
Consider the following program fragment in the assembly language of a certain hypothetical processor. The processor has three general purpose registers $R1, R2$and $R3$. ...
5.8k
views
comment edited
Apr 20, 2021
CO and Architecture
gate1999
co-and-architecture
machine-instruction
normal
descriptive
+
–
4
answers
11
MadeEasy Subject Test: CO & Architecture - Dma
Consider $1 \text{ MBPS}$ hard disk is interfaced to the processor in a cycle stealing mode of $\text{DMA}$ whenever $64$ bytes of the data is available in the buffer then it is transferred to the main memory. Processor word length is $64$ bits ... $\text{CPU}$ time is consumed for the $\text{DMA}$ operation is ________ (in $\%$).
Consider $1 \text{ MBPS}$ hard disk is interfaced to the processor in a cycle stealing mode of $\text{DMA}$ whenever $64$ bytes of the data is available in the buffer the...
4.0k
views
commented
Apr 19, 2021
CO and Architecture
co-and-architecture
made-easy-test-series
dma
+
–
4
answers
12
GATE CSE 2009 | Question: 8, UGCNET-June2012-III: 58
A CPU generally handles an interrupt by executing an interrupt service routine: As soon as an interrupt is raised. By checking the interrupt register at the end of fetch cycle. By checking the interrupt register after finishing the execution of the current instruction. By checking the interrupt register at fixed time intervals.
A CPU generally handles an interrupt by executing an interrupt service routine:As soon as an interrupt is raised.By checking the interrupt register at the end of fetch cy...
15.8k
views
commented
Apr 19, 2021
CO and Architecture
gatecse-2009
co-and-architecture
interrupts
normal
ugcnetcse-june2012-paper3
+
–
3
answers
13
GATE CSE 2021 Set 2 | Question: 16
Consider a complete binary tree with $7$ nodes. Let $A$ denote the set of first $3$ elements obtained by performing Breadth-First Search $\text{(BFS)}$ starting from the root. Let $B$ denote the set of first $3$ elements obtained by performing Depth-First Search $\text{(DFS)}$ starting from the root. The value of $\mid A-B \mid $ is _____________
Consider a complete binary tree with $7$ nodes. Let $A$ denote the set of first $3$ elements obtained by performing Breadth-First Search $\text{(BFS)}$ starting from the ...
11.0k
views
answer edited
Apr 18, 2021
DS
gatecse-2021-set2
numerical-answers
data-structures
binary-tree
1-mark
+
–
9
answers
14
GATE CSE 2017 Set 1 | Question: 51
Consider a $2$-way set associative cache with $256$ blocks and uses $\text{LRU}$ replacement. Initially the cache is empty. Conflict misses are those misses which occur due to the contention of multiple blocks for the same cache set. Compulsory ... $10$ times. The number of conflict misses experienced by the cache is _________ .
Consider a $2$-way set associative cache with $256$ blocks and uses $\text{LRU}$ replacement. Initially the cache is empty. Conflict misses are those misses which occur d...
38.4k
views
commented
Apr 18, 2021
CO and Architecture
gatecse-2017-set1
co-and-architecture
cache-memory
conflict-misses
normal
numerical-answers
+
–
2
answers
15
GATE IT 2007 | Question: 36
The floating point unit of a processor using a design $D$ takes $2t$ cycles compared to $t$ cycles taken by the fixed point unit. There are two more design suggestions $D_1$ and $D_2$. $D_1$ uses $30\%$ more cycles for fixed point unit but $30\%$ less cycles for floating ... $D_1 > D > D_2$ $D_2 > D > D_1$ $D > D_2 > D_1$ $D > D_1 > D_2$
The floating point unit of a processor using a design $D$ takes $2t$ cycles compared to $t$ cycles taken by the fixed point unit. There are two more design suggestions $D...
5.8k
views
commented
Apr 18, 2021
CO and Architecture
gateit-2007
co-and-architecture
normal
clock-frequency
+
–
13
answers
16
GATE CSE 2016 Set 2 | Question: 50
A file system uses an in-memory cache to cache disk blocks. The miss rate of the cache is shown in the figure. The latency to read a block from the cache is $1$ ms and to read a block from the disk is $10$ ms. Assume that the cost ... in multiples of $10$ MB. The smallest cache size required to ensure an average read latency of less than $6$ ms is _________ MB.
A file system uses an in-memory cache to cache disk blocks. The miss rate of the cache is shown in the figure. The latency to read a block from the cache is $1$ ms and to...
14.9k
views
commented
Apr 18, 2021
CO and Architecture
gatecse-2016-set2
co-and-architecture
cache-memory
normal
numerical-answers
+
–
1
answer
17
GATE CSE 2007 | Question: 10
Consider a $4$-way set associative cache consisting of $128$ lines with a line size of $64$ words. The CPU generates a $20-bit$ address of a word in main memory. The number of bits in the TAG, LINE and WORD fields are respectively: $9, 6, 5$ $7, 7, 6$ $7, 5, 8$ $9, 5, 6$
Consider a $4$-way set associative cache consisting of $128$ lines with a line size of $64$ words. The CPU generates a $20-bit$ address of a word in main memory. The numb...
13.0k
views
commented
Apr 17, 2021
CO and Architecture
gatecse-2007
co-and-architecture
cache-memory
normal
+
–
5
answers
18
GATE CSE 1998 | Question: 18
For a set-associative Cache organization, the parameters are as follows: ... $1 \leq m \leq l$. Give the value of the hit ratio for $l = 1$.
For a set-associative Cache organization, the parameters are as follows:$$\begin{array}{|c|l|} \hline \text {$t _c$} & \text{Cache Access Time }\\\hline \text{$t _m$} &...
11.9k
views
commented
Apr 17, 2021
CO and Architecture
gate1998
co-and-architecture
cache-memory
descriptive
+
–
4
answers
19
GATE CSE 1992 | Question: 5-a
The access times of the main memory and the Cache memory, in a computer system, are $500$ n sec and $50$ nsec, respectively. It is estimated that $80\%$ of the main memory request are for read the rest for write. The hit ratio for ... policy (where both main and cache memories are updated simultaneously) is used. Determine the average time of the main memory (in ns).
The access times of the main memory and the Cache memory, in a computer system, are $500$ n sec and $50$ nsec, respectively. It is estimated that $80\%$ of the main memor...
23.8k
views
commented
Apr 17, 2021
CO and Architecture
gate1992
co-and-architecture
cache-memory
normal
numerical-answers
+
–
1
answer
20
GATE CSE 2005 | Question: 66
Match each of the high level language statements given on the left hand side with the most natural addressing mode from those listed on the right hand side. ... $(1, b), (2, c), (3, a)$ $(1, a), (2, b), (3, c)$
Match each of the high level language statements given on the left hand side with the most natural addressing mode from those listed on the right hand side.$$\begin{array...
6.8k
views
comment edited
Apr 17, 2021
CO and Architecture
gatecse-2005
co-and-architecture
addressing-modes
match-the-following
easy
+
–
3
answers
21
GATE CSE 1993 | Question: 10
The instruction format of a CPU is: $\text{Mode}$ and $\text{RegR}$ together specify the operand. $\text{RegR}$ specifies a CPU register and $\text{Mode}$ specifies an addressing mode. In particular, $\text{Mode}=2$ specifies that ... address of the operand? Assuming that is a non-jump instruction, what are the contents of PC after the execution of this instruction?
The instruction format of a CPU is:$\text{Mode}$ and $\text{RegR}$ together specify the operand. $\text{RegR}$ specifies a CPU register and $\text{Mode}$ specifies an add...
7.0k
views
commented
Apr 17, 2021
CO and Architecture
gate1993
co-and-architecture
addressing-modes
normal
descriptive
+
–
1
answer
22
GATE CSE 1988 | Question: 9iii
In the program scheme given below indicate the instructions containing any operand needing relocation for position independent behaviour. Justify your answer. ...
In the program scheme given below indicate the instructions containing any operand needing relocation for position independent behaviour. Justify your answer.$$\begin{arr...
3.5k
views
commented
Apr 17, 2021
CO and Architecture
gate1988
normal
descriptive
co-and-architecture
addressing-modes
+
–
1
answer
23
how many stall cycles in this system on cache miss ?
Directly coming to the question...(its a linked data type qstn) A pipelined processor with separate instruction and data cache has 5 stages with a cycle time of 30 ns. It is used with copy-back data cache with block size of 1 word. ... answer given is different. And based on 1st qstn only you are able to solve second one. Where am I going wrong??
Directly coming to the question...(its a linked data type qstn)A pipelined processor with separate instruction and data cache has 5 stages with a cycle time of 30 ns. It ...
1.2k
views
commented
Apr 16, 2021
CO and Architecture
co-and-architecture
cache-memory
pipelining
+
–
4
answers
24
GATE CSE 2021 Set 2 | Question: 53
Consider a pipelined processor with $5$ stages, $\text{Instruction Fetch} (\textsf{IF})$, $\text{Instruction Decode} \textsf{(ID)}$, $\text{Execute } \textsf{(EX)}$, $\text{Memory Access } \textsf{(MEM)}$ ... $\textit{Speedup} $ achieved in executing the given instruction sequence on the pipelined processor (rounded to $2$ decimal places) is _____________
Consider a pipelined processor with $5$ stages, $\text{Instruction Fetch} (\textsf{IF})$, $\text{Instruction Decode} \textsf{(ID)}$, $\text{Execute } \textsf{(EX)}$, $\te...
15.1k
views
commented
Apr 16, 2021
CO and Architecture
gatecse-2021-set2
co-and-architecture
pipelining
instruction-execution
numerical-answers
2-marks
+
–
4
answers
25
MadeEasy Test Series: CO & Architecture - Cache Memory
Array A contains $256$ elements of $4$ bytes each. Its first element is stored at physical address $4,096.$ Array B contains $512$ elements of $4$ bytes each. Its first element is stored at physical address $8,192.$ Assume that only arrays A and B can ... to memory if the cache has a write-through policy? $a) 0$ $b) 256$ $c) 1,024$ $d) 2,048$
Array A contains $256$ elements of $4$ bytes each. Its first element is stored at physical address $4,096.$ Array B contains $512$ elements of $4$ bytes each. Its first e...
2.6k
views
commented
Apr 15, 2021
CO and Architecture
made-easy-test-series
co-and-architecture
cache-memory
+
–
4
answers
26
GATE CSE 2000 | Question: 2.14
Consider the values of $A = 2.0 \times 10^{30}, B = -2.0 \times 10^{30}, C = 1.0,$ and the sequence X:= A + B Y:= A + C X:= X + C Y:= Y + B executed on a computer where floating point numbers are represented with $32$ bits. The values for $X$ and $Y$ will be $X = 1.0, Y = 1.0$ $X = 1.0, Y = 0.0$ $X = 0.0, Y = 1.0$ $X = 0.0, Y = 0.0$
Consider the values of $A = 2.0 \times 10^{30}, B = -2.0 \times 10^{30}, C = 1.0,$ and the sequence X:= A + B Y:= A + C X:= X + C Y:= Y + Bexecuted on a computer where fl...
11.8k
views
commented
Apr 12, 2021
Digital Logic
gatecse-2000
digital-logic
number-representation
normal
+
–
5
answers
27
GATE CSE 2003 | Question: 44
A $\text{1-input}$, $\text{2-output}$ synchronous sequential circuit behaves as follows: Let $z_k, n_k$ denote the number of $0's$ and $1's$ respectively in initial $k$ bits of the input $(z_k+n_k=k)$. The circuit outputs $00$ until one of the ... is $01$. What is the minimum number of states required in the state transition graph of the above circuit? $5$ $6$ $7$ $8$
A $\text{1-input}$, $\text{2-output}$ synchronous sequential circuit behaves as follows:Let $z_k, n_k$ denote the number of $0’s$ and $1’s$ respectively in initial $k...
11.8k
views
commented
Apr 12, 2021
Digital Logic
gatecse-2003
digital-logic
synchronous-asynchronous-circuits
normal
+
–
3
answers
28
GATE CSE 1998 | Question: 16
Design a synchronous counter to go through the following states:$1, 4, 2, 3, 1, 4, 2, 3, 1, 4 \dots $
Design a synchronous counter to go through the following states:$$1, 4, 2, 3, 1, 4, 2, 3, 1, 4 \dots $$
5.0k
views
commented
Apr 12, 2021
Digital Logic
gate1998
digital-logic
normal
descriptive
synchronous-asynchronous-circuits
+
–
4
answers
29
GATE IT 2005 | Question: 9
A dynamic RAM has a memory cycle time of $64$ $\text{nsec}$. It has to be refreshed $100$ times per msec and each refresh takes $100$ $\text{nsec}$ . What percentage of the memory cycle time is used for refreshing? $10$ $6.4$ $1$ $0.64$
A dynamic RAM has a memory cycle time of $64$ $\text{nsec}$. It has to be refreshed $100$ times per msec and each refresh takes $100$ $\text{nsec}$ . What percentage of t...
10.5k
views
commented
Apr 12, 2021
Digital Logic
gateit-2005
digital-logic
memory-interfacing
normal
+
–
9
answers
30
GATE CSE 1997 | Question: 5.1
Let $f(x, y, z)=\bar{x} + \bar{y}x + xz$ be a switching function. Which one of the following is valid? $\bar{y} x$ is a prime implicant of $f$ $xz$ is a minterm of $f$ $xz$ is an implicant of $f$ $y$ is a prime implicant of $f$
Let $f(x, y, z)=\bar{x} + \bar{y}x + xz$ be a switching function. Which one of the following is valid?$\bar{y} x$ is a prime implicant of $f$$xz$ is a minterm of $f$$xz$ ...
15.7k
views
commented
Apr 11, 2021
Digital Logic
gate1997
digital-logic
normal
prime-implicants
+
–
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