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1 votes
1 answer
211
ISRO 2007-ECE Up counter
A 4-bit presetable UP counter has preset input 0101. The preset operation takes place as soon as the counter reaches 1111. The modulus of the counter is a) 5 b) 10 c) 11 d) 15
A 4-bit presetable UP counter has preset input 0101. The preset operation takes place as soon as the counter reaches 1111. The modulus of the counter isa) 5b) 10c) 11d) 1...
0 votes
2 answers
212
ISRO 2007-ECE : Binary Codes
The logic circuit given below converts a binary code Y1 Y2 Y3 into a) Excess -3 code b) Gray code c) BCD code d) Hamming code
The logic circuit given below converts a binary code Y1 Y2 Y3 intoa) Excess -3 codeb) Gray codec) BCD coded) Hamming code
0 votes
1 answer
213
ISRO 2007-ECE Boolean Dual
For the identity $AB + A' C + BC = AB + A' C$, the dual form is $(A+B) (A'+C)(B+C)= (A+B)(A'+C)$ $(A'+ B') ( A' + C') (B'+C')= (A'+ B') (A +C')$ $(A+B) (A'+C) (B+C) = (A'+ B') (A+ C')$ $A'B'+AC'+ B'C'= A'B'+AC'$
For the identity $AB + A' C + BC = AB + A' C$, the dual form is$(A+B) (A'+C)(B+C)= (A+B)(A'+C)$$(A'+ B') ( A' + C') (B'+C')= (A'+ B') (A +C')$$(A+B) (A'+C) (B+C) = (A'+ B...
1 votes
1 answer
214
ISRO 2007- ECE Combinational circuit
The Boolean expression for the output of the logic circuit shown in the figure is $Y=AB+ A'B'+C$ $Y= AB+A'B'+ C'$ $Y=A B'+ A'B+C$ $Y=AB+ A'B+ C'$
The Boolean expression for the output of the logic circuit shown in the figure is$Y=AB+ A'B'+C$$Y= AB+A'B'+ C'$$Y=A B'+ A'B+C$$Y=AB+ A'B+ C'$
0 votes
2 answers
215
ISRO 2007-ECE Conversion to binaty number
Which of the following binary number is equal to octal number 66.3 a) 101101.100 b) 1101111.111 c) 111111.1111 d) 110110.011
Which of the following binary number is equal to octal number 66.3 a) 101101.100b) 1101111.111c) 111111.1111d) 110110.011
0 votes
1 answer
216
ISRO 2007- ECE Digital logic
The circuit is a a) Monostable MV b) Astable MV c) Adder d) SR FF
The circuit is aa) Monostable MVb) Astable MVc) Adderd) SR FF
0 votes
1 answer
218
ISRO 2007-ECE Half Adder Circuit
A half adder can be constructed using two $2$-input logic gates. One of them is an $\text{AND}$-gate, the other is $\text{OR}$ $\text{NAND}$ $\text{NOR}$ $\text{EX-OR}$
A half adder can be constructed using two $2$-input logic gates. One of them is an $\text{AND}$-gate, the other is$\text{OR}$$\text{NAND}$$\text{NOR}$$\text{EX-OR}$
0 votes
1 answer
219
ISRO 2008- ECE adjoint Matrix
The matrix is its own adjoint. The value of x will be (a) 5 (b) 3 (c) -3 (d) -5
The matrix is its own adjoint. The value of x will be(a) 5 (b) 3 (c) -3 (d) -5
1 votes
1 answer
220
ISRO 2008- ECE GOTO statement
The "go to statement" causes control to go to (a) An operator (b) A label (c) A variable (d) A function
The "go to statement" causes control to go to(a) An operator(b) A label(c) A variable(d) A function
0 votes
2 answers
221
ISRO 2008-ECE exit() function
The library function exit ( ) causes as exit from (a) the loop in which it occurs (b) the block is which it occurs (c) the functions in which it occurs (d) the progam in which it occurs
The library function exit ( ) causes as exit from (a) the loop in which it occurs(b) the block is which it occurs(c) the functions in which it occurs(d) the progam in whi...
0 votes
1 answer
222
ISRO 2008-ECE programming
A program having features such as data abstraction, encapsulation and data hiding, polymorphism inheritance is called (a) Structured program (b) Object oriented program (c) Open source program (d) Real time program
A program having features such as data abstraction, encapsulation and data hiding, polymorphism inheritance is called(a) Structured program(b) Object oriented program(c) ...
1 votes
0 answers
224
ISRO 2008-ECE Integration
0 votes
1 answer
225
ISRO 2008-ECE Moore model for squntial circuits
Which of the following represents the Moore model for sequential circuits?
Which of the following represents the Moore model for sequential circuits?
0 votes
1 answer
226
ISRO 2008-ECE Computer architecture
Digital signal processors use a computer architecture derived from (a) Harvard Architecture (b) Von-Neumann Architecture (c) Cray Architecture (d) None of the above
Digital signal processors use a computer architecture derived from(a) Harvard Architecture(b) Von-Neumann Architecture(c) Cray Architecture(d) None of the above
0 votes
2 answers
228
ISRO 2008- ECE PROM
A programmable device (PROM) is (a) programmable OR and fixed AND array (b) programmable AND and fixed OR array (c) programmable AND and programmable OR array (d) none
A programmable device (PROM) is(a) programmable OR and fixed AND array(b) programmable AND and fixed OR array(c) programmable AND and programmable OR array(d) none
0 votes
1 answer
229
ISRO 2008-ECE - Ripple counter
In a ripple counter how many changes in state happen when count changes from 7 to 8? (a)$1$ (b)$2$ (c)$3$ (d)$4$
In a ripple counter how many changes in state happen when count changes from 7 to 8?(a)$1$(b)$2$(c)$3$(d)$4$
3 votes
2 answers
230
ISRO 2008- ECE minimum number of NAND Gates
Minimum number of 2-input NAND gates that will be required to implement the function: Y = AB + CD + EF is (a) 4 (b) 5 (c) 6 (d) 7
Minimum number of 2-input NAND gates that will be required to implement the function: Y = AB + CD + EF is(a) 4(b) 5(c) 6(d) 7
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