Login
Register
Dark Mode
Brightness
Profile
Edit Profile
Messages
My favorites
My Updates
Logout
Filter
sidsunny
Wall
Recent activity
All questions
All answers
Exams Taken
All Blogs
Recent activity by sidsunny
2
answers
1
MadeEasy Subject Test: CO & Architecture - Dma
I have gone through these types of questions but I'm unable to understand. how to appraoch these questions? And during the dma transfer, cpu is considered to be idle. before and after that it can do its own work. Where am I wrong?
I have gone through these types of questions but I'm unable to understand. how to appraoch these questions? And during the dma transfer, cpu is considered to be idle. bef...
829
views
answer selected
Feb 10, 2017
CO and Architecture
made-easy-test-series
co-and-architecture
dma
+
–
1
answer
2
MadeEasy Subject Test: Digital Logic - Digital Counter
382
views
asked
Feb 1, 2017
Digital Logic
made-easy-test-series
digital-logic
digital-counter
multiplexer
+
–
0
answers
3
madeeasy
156
views
asked
Feb 1, 2017
Digital Logic
digital-logic
+
–
1
answer
4
MadeEasy Subject Test: Databases - Transactions
Here T1 T2 T4 T5 will come in this order only and for T3 we have 5 positions So number of schedules will be 5 which are view eq to given schedule. But ans given is 10
Here T1 T2 T4 T5 will come in this order only and for T3 we have 5 positionsSo number of schedules will be 5 which are view eq to given schedule.But ans given is 10
221
views
answer edited
Jan 31, 2017
Databases
made-easy-test-series
databases
transaction-and-concurrency
+
–
1
answer
5
madeeasy
306
views
commented
Jan 29, 2017
Computer Networks
computer-networks
+
–
4
answers
6
GATE CSE 2015 Set 2 | Question: 49
Consider a typical disk that rotates at $15000$ rotations per minute (RPM) and has a transfer rate of $50 \times 10^6$ bytes/sec. If the average seek time of the disk is twice the average rotational delay and the controller's transfer time ... the disk transfer time, the average time (in milliseconds) to read or write a $512$-byte sector of the disk is _____
Consider a typical disk that rotates at $15000$ rotations per minute (RPM) and has a transfer rate of $50 \times 10^6$ bytes/sec. If the average seek time of the disk is ...
17.5k
views
commented
Jan 28, 2017
Operating System
gatecse-2015-set2
operating-system
disk
normal
numerical-answers
+
–
1
answer
7
MadeEasy CBT 2017: CO & Architecture - Cache Memory
875
views
commented
Jan 26, 2017
CO and Architecture
made-easy-test-series
cbt-2017
co-and-architecture
cache-memory
+
–
0
answers
8
madeeasy
How are the delay registers to be considered?
How are the delay registers to be considered?
225
views
asked
Jan 26, 2017
CO and Architecture
made-easy-test-series
co-and-architecture
pipelining
+
–
3
answers
9
page replacement
An 8 byte, 2-way set associative (using LRU replacement) with 2 byte blocks receives requests for the following addresses (represented in binary): 0110, 0000, 0010, 0001, 0011, 0100, 1001, 0000, 1010, 1111, 0111 . How page replacement is done?What are the types of misses occured in this case?
An 8 byte, 2-way set associative (using LRU replacement) with 2 byte blocks receives requests for the following addresses (represented in binary): 0110, 0000, 0010, 0001,...
3.3k
views
commented
Jan 26, 2017
CO and Architecture
co-and-architecture
cache-memory
least-recently-used
misses
+
–
1
answer
10
MadeEasy Subject Test: Compiler Design - Parsing
First(P) = {+, *, t, epsilon, id} AND Follow(P) = {dollar,id} according to me. In that case M[P, DOLLAR] should have P -> QR
First(P) = {+, *, t, epsilon, id} AND Follow(P) = {dollar,id} according to me. In that case M[P, DOLLAR] should have P - QR
375
views
commented
Jan 26, 2017
Compiler Design
made-easy-test-series
compiler-design
parsing
ll-parser
+
–
1
answer
11
MadeEasy Subject Test: Digital Logic - Booths Algorithm
I understand booth's algorithm, but what is the meaning of this question?
I understand booth's algorithm, but what is the meaning of this question?
3.5k
views
commented
Jan 26, 2017
Digital Logic
made-easy-test-series
digital-logic
booths-algorithm
+
–
1
answer
12
madeeasy
My question is how does cache block size affect the placement of blocks/addresses in cache? Example: here 2 word cache block vs 1 word cache block size. What will be the difference?
My question is how does cache block size affect the placement of blocks/addresses in cache? Example: here 2 word cache block vs 1 word cache block size. What will be the ...
286
views
commented
Jan 26, 2017
CO and Architecture
made-easy-test-series
co-and-architecture
cache-memory
+
–
2
answers
13
what is the complexity
430
views
answer edited
Jan 19, 2017
Algorithms
algorithms
time-complexity
test-series
+
–
1
answer
14
No of tuples
Ans given: 100
Ans given: 100
898
views
commented
Jan 12, 2017
Databases
databases
natural-join
+
–
1
answer
15
Madeeasy dbms test
370
views
asked
Jan 9, 2017
Databases
databases
+
–
1
answer
16
MadeEasy Full test question
A packet of 10 bulbs is known to include 2 bulbs that are defective. If 4 bulbs are randomly chosen and tested, the probability of finding among them not more than 1 defective bulb is ____.
A packet of 10 bulbs is known to include 2 bulbs that are defective. If 4 bulbs are randomly chosen and tested, the probability of finding among them not more than 1 defe...
1.3k
views
commented
Jan 7, 2017
Combinatory
probability
+
–
4
answers
17
GATE CSE 2000 | Question: 2.14
Consider the values of $A = 2.0 \times 10^{30}, B = -2.0 \times 10^{30}, C = 1.0,$ and the sequence X:= A + B Y:= A + C X:= X + C Y:= Y + B executed on a computer where floating point numbers are represented with $32$ bits. The values for $X$ and $Y$ will be $X = 1.0, Y = 1.0$ $X = 1.0, Y = 0.0$ $X = 0.0, Y = 1.0$ $X = 0.0, Y = 0.0$
Consider the values of $A = 2.0 \times 10^{30}, B = -2.0 \times 10^{30}, C = 1.0,$ and the sequence X:= A + B Y:= A + C X:= X + C Y:= Y + Bexecuted on a computer where fl...
11.8k
views
commented
Dec 29, 2016
Digital Logic
gatecse-2000
digital-logic
number-representation
normal
+
–
3
answers
18
GATE CSE 1997 | Question: 3.6
The correct matching for the following pairs is: ... $\text{A-4 B-3 C-2 D-1}$ $\text{A-2 B-4 C-1 D-3}$ $\text{A-3 B-4 C-3 D-2}$
The correct matching for the following pairs is:$$\small \begin{array}{cl|cl}\hline \text{(A)} &\text{Disk Scheduling} & \text{(1)} &\text{Round robin} \\\hline \text{...
5.6k
views
commented
Dec 17, 2016
Operating System
gate1997
operating-system
normal
disk-scheduling
match-the-following
+
–
4
answers
19
GATE CSE 2016 Set 2 | Question: 41
In an adjacency list representation of an undirected simple graph $G=(V, E)$, each edge $(u, v)$ has two adjacency list entries: $[v]$ in the adjacency list of $u$, and $[u]$ in the adjacency list of $v$. These are called twins of each other. A twin pointer ... $\Theta\left(n+m\right)$ $\Theta\left(m^{2}\right)$ $\Theta\left(n^{4}\right)$
In an adjacency list representation of an undirected simple graph $G=(V, E)$, each edge $(u, v)$ has two adjacency list entries: $[v]$ in the adjacency list of $u$, and $...
19.5k
views
commented
Dec 13, 2016
Algorithms
gatecse-2016-set2
algorithms
graph-algorithms
normal
+
–
5
answers
20
GATE CSE 2007 | Question: 47
Consider the process of inserting an element into a $Max \: Heap$, where the $Max \: Heap$ is represented by an $array$. Suppose we perform a binary search on the path from the new leaf to the root to find the position for the newly inserted element, the number of $comparisons$ performed is: $\Theta(\log_2n)$ $\Theta(\log_2\log_2n)$ $\Theta(n)$ $\Theta(n\log_2n)$
Consider the process of inserting an element into a $Max \: Heap$, where the $Max \: Heap$ is represented by an $array$. Suppose we perform a binary search on the path fr...
19.3k
views
commented
Dec 12, 2016
DS
gatecse-2007
data-structures
binary-heap
normal
+
–
1
answer
21
sockets
Why we not apply bind() at the client side?
Why we not apply bind() at the client side?
845
views
answered
Dec 6, 2016
Computer Networks
computer-networks
+
–
2
answers
22
MadeEasy Test Series: Compiler Design - Syntax Directed Translation
963
views
commented
Nov 23, 2016
Compiler Design
made-easy-test-series
compiler-design
syntax-directed-translation
+
–
1
answer
23
mathematical logic
(pr)(st) p t 1. (pr)(st) Premise 2. p Premise 3. pr 2, Addition 4. st 1, 3 Modus Ponens 5. t 4, Simplification I am not getting two rules 1. addition (p→(pr)) 2. Simplification ((st)→t) How and where we can apply?
(pr)(st)p t1. (pr)(st)Premise2. pPremise3. pr2, Addition4. st1, 3 Modus Ponens5. t4, SimplificationI am not getting two rules 1. addition (p→(pr)) ...
287
views
answered
Nov 16, 2016
Mathematical Logic
mathematical-logic
propositional-logic
+
–
Email or Username
Show
Hide
Password
I forgot my password
Remember
Log in
Register