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Questions by sidsunny
0
votes
1
answer
1
MadeEasy Subject Test: Digital Logic - Digital Counter
388
views
asked
Feb 1, 2017
Digital Logic
made-easy-test-series
digital-logic
digital-counter
multiplexer
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–
0
votes
0
answers
2
madeeasy
160
views
asked
Feb 1, 2017
Digital Logic
digital-logic
+
–
0
votes
1
answer
3
madeeasy
324
views
asked
Jan 29, 2017
Computer Networks
computer-networks
+
–
1
votes
2
answers
4
MadeEasy Subject Test: CO & Architecture - Dma
I have gone through these types of questions but I'm unable to understand. how to appraoch these questions? And during the dma transfer, cpu is considered to be idle. before and after that it can do its own work. Where am I wrong?
I have gone through these types of questions but I'm unable to understand. how to appraoch these questions? And during the dma transfer, cpu is considered to be idle. bef...
863
views
asked
Jan 26, 2017
CO and Architecture
made-easy-test-series
co-and-architecture
dma
+
–
0
votes
0
answers
5
madeeasy
How are the delay registers to be considered?
How are the delay registers to be considered?
232
views
asked
Jan 26, 2017
CO and Architecture
made-easy-test-series
co-and-architecture
pipelining
+
–
0
votes
1
answer
6
MadeEasy Subject Test: Compiler Design - Parsing
First(P) = {+, *, t, epsilon, id} AND Follow(P) = {dollar,id} according to me. In that case M[P, DOLLAR] should have P -> QR
First(P) = {+, *, t, epsilon, id} AND Follow(P) = {dollar,id} according to me. In that case M[P, DOLLAR] should have P - QR
382
views
asked
Jan 26, 2017
Compiler Design
made-easy-test-series
compiler-design
parsing
ll-parser
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–
0
votes
1
answer
7
madeeasy
My question is how does cache block size affect the placement of blocks/addresses in cache? Example: here 2 word cache block vs 1 word cache block size. What will be the difference?
My question is how does cache block size affect the placement of blocks/addresses in cache? Example: here 2 word cache block vs 1 word cache block size. What will be the ...
302
views
asked
Jan 26, 2017
CO and Architecture
made-easy-test-series
co-and-architecture
cache-memory
+
–
1
votes
1
answer
8
MadeEasy Subject Test: Digital Logic - Booths Algorithm
I understand booth's algorithm, but what is the meaning of this question?
I understand booth's algorithm, but what is the meaning of this question?
3.5k
views
asked
Jan 26, 2017
Digital Logic
made-easy-test-series
digital-logic
booths-algorithm
+
–
1
votes
1
answer
9
Madeeasy dbms test
378
views
asked
Jan 9, 2017
Databases
databases
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–
1
votes
1
answer
10
MadeEasy Full test question
A packet of 10 bulbs is known to include 2 bulbs that are defective. If 4 bulbs are randomly chosen and tested, the probability of finding among them not more than 1 defective bulb is ____.
A packet of 10 bulbs is known to include 2 bulbs that are defective. If 4 bulbs are randomly chosen and tested, the probability of finding among them not more than 1 defe...
1.4k
views
asked
Jan 7, 2017
Combinatory
probability
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