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Recent activity by vix28
2
answers
1
DBMS GATEBOOK Exam
R(A,B,C,D,E) with functional dependencies AE , E D , CDA and BCE. Let the decomposition be with schemas R(A,B,C) , R(B,C,D) ,and R(C,D,E) . Which of the following is true about decomposition? (A) Lossless join and dependency preserving (B) Lossless join but not dependency preserving (C) Dependency preserving but not lossless join (D) Neither lossless nor dependency preserving
R(A,B,C,D,E) with functional dependencies AE , E D , CDA and BCE. Let the decomposition be with schemas R(A,B,C) , R(B,C,D) ,and R(C,D,E) .Which of the following is true ...
566
views
commented
Sep 20, 2016
2
answers
2
Tuple Relational Calculus
I believe since the variable 't' is a free variable, so option three should also be right. Second option is also correct?
I believe since the variable 't' is a free variable, so option three should also be right. Second option is also correct?
625
views
answered
Sep 13, 2016
Databases
relational-calculus
databases
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–
0
answers
3
Regarding PHD at IITs
In the cutoff list presented by gateoverflow , for direct PHD at IITs the criteria written is mostly x% in btech+gate score.In some of the places its specified that gate score is above 600 etc. So how do we know the exact cutoff for PHDs at IITs. Upto what gate score do they usually call. Please confirm. Thanks.
In the cutoff list presented by gateoverflow , for direct PHD at IITs the criteria written is mostly x% in btech+gate score.In some of the places its specified that gate ...
6.4k
views
commented
Sep 9, 2016
2
answers
4
serializablity and recoverability of schedules
1) T1: R(X), T2: W(X), T1: W(X), T2: Abort, T1: Commit 2) T1: W(X), T2: R(X), T1: W(X), T2: Abort, T1: Commit 3) T1: W(X), T2: R(X), T1: W(X), T2: ... : Abort Can anyone explain whether these schedules are serializable, conflict-serializable, view serializable, recoverable, avoids-cascading-aborts, and strict? The abort operation actually bugging me.
1) T1: R(X), T2: W(X), T1: W(X), T2: Abort, T1: Commit2) T1: W(X), T2: R(X), T1: W(X), T2: Abort, T1: Commit3) T1: W(X), T2: R(X), T1: W(X), T2: Commit, T1: AbortCan anyo...
12.5k
views
commented
Sep 8, 2016
Databases
transaction-and-concurrency
concurrency
conflict-serializable
view-serializable
databases
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–
3
answers
5
Algorithms
Consider the following code fragment for i=1 to n/2 do for j=i to n-1 do for k=1 to j do output ''foobar'' Assume $n$ is even Let $T(n)$ denote the number of times 'foobar' is printed as a function of $n$. Express $T(n)$ as three nested summations. Simplify the summation. Show your work.
Consider the following code fragment for i=1 to n/2 do for j=i to n-1 do for k=1 to j do output ''foobar''Assume $n$ is even Let $T(n)$ denote the number of times '...
1.4k
views
commented
Aug 21, 2016
Algorithms
time-complexity
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–
1
answer
6
What is the minimum pumping length of the following languages
This is from the first chapter questions of Sipser's book on TOC. I am stuck in some of the questions where we are asked to find the pumping length of the following languages. Find the minimum pumping length of the following regular languages:- L=$0^*1^+0^+1^* \cup \ 10^*1$ L=001 U 0*1* L=0*1* L=10 (11* 0)* 0 L= ∊
This is from the first chapter questions of Sipser's book on TOC. I am stuck in some of the questions where we are asked to find the pumping length of the following langu...
18.1k
views
commented
Aug 9, 2016
Theory of Computation
theory-of-computation
pumping-lemma
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–
3
answers
7
equality of regular expressions
Q which of the following pair of regular expressions are equal a)a* & ((aa)* + (aa0)*)* b)(r+s)* & (rs)* c)(rr)* & r*r* d)(r1(r1+r2)*)* & r1(r1+r2) answer given is option D but it think option D should be modified to (r1(r1+r2)*)* & r1*(r1+r2)* for being it correct.
Qwhich of the following pair of regular expressions are equala)a* & ((aa)* + (aa0)*)*b)(r+s)* & (rs)*c)(rr)* & r*r*d)(r1(r1+r2)*)* & r1(r1+r2)answer given is option D but...
618
views
commented
Jul 29, 2016
Theory of Computation
theory-of-computation
regular-expression
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–
1
answer
8
What is a desirable choice for the partitioning element in quick sort?
A desirable choice for the partitioning element in quick sort is (A) First element of the list (B) Last element of the list (C) Randomly chosen element of the list (D) Median of the list
A desirable choice for the partitioning element in quick sort is(A) First element of the list(B) Last element of the list(C) Randomly chosen element of the list(D) Median...
5.9k
views
commented
Jul 24, 2016
Algorithms
sorting
algorithms
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–
4
answers
9
GATE CSE 2003 | Question: 77
A uni-processor computer system only has two processes, both of which alternate $10$ $\text{ms}$ CPU bursts with $90$ $\text{ms}$ I/O bursts. Both the processes were created at nearly the same time. The I/O of both processes ... Static priority scheduling with different priorities for the two processes Round robin scheduling with a time quantum of $5$ $\text{ms}$
A uni-processor computer system only has two processes, both of which alternate $10$ $\text{ms}$ CPU bursts with $90$ $\text{ms}$ I/O bursts. Both the processes were crea...
19.8k
views
commented
Jul 1, 2016
Operating System
gatecse-2003
operating-system
process-scheduling
normal
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–
1
answer
10
validity of relational algebra query
Let R and S be two relations, and l be an attribute common to R and S. Let c be a condition over the attributes common to R and S. Prove or disprove the following:
Let R and S be two relations, and l be an attribute common to R and S.Let c be a condition over the attributes common to R and S. Prove ordisprove the following:
479
views
asked
Apr 26, 2016
Databases
relational-algebra
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–
3
answers
11
Calculation of context switch overhead - ISI KOL -2014 Qstn 6(a)
Consider three processes, P1, P2, and P3. Their start times and execution times are given below Let x be the amount of time taken by the kernel to complete a context switch from any process Pi to Pj . For what ... P1, P2, P3 be reduced by choosing a Shortest Remaining Time First scheduling policy over a Shortest Job First policy?
Consider three processes, P1, P2, and P3. Their start times and executiontimes are given belowLet x be the amount of time taken by the kernel to complete a contextswitch ...
847
views
commented
Apr 26, 2016
Operating System
operating-system
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–
4
answers
12
multilevel paging technique
A virtual memory system is able to support virtual address space of 256 GB. An entry in the page table is 4 bytes long. (i) Calculate the minimum page size required for a three-level paging scheme. (ii) Draw a diagram indicating how the bits of a ... (and how many) are used to index the page tables at each level, and which bits form the page offset for the case above.
A virtual memory system is able to support virtual address space of 256 GB. An entryin the page table is 4 bytes long.(i) Calculate the minimum page size required for a t...
7.8k
views
commented
Apr 24, 2016
CO and Architecture
co-and-architecture
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–
0
answers
13
Time taken for the entire message to reach from source to destination
A 64000-byte message is to be transmitted over a 2-hop path in a storeand- forward packet-switching network. The network limits packets to a maximum size of 2032 bytes including a 32-byte header. The transmission lines in the ... + 31*32.512 msec= 1115.398 msec Can anyone confirm this answer. Please help if any error is there .
A 64000-byte message is to be transmitted over a 2-hop path in a storeand- forward packet-switching network. The network limits packets to a maximum size of 2032 bytes in...
3.6k
views
asked
Apr 12, 2016
Computer Networks
computer-networks
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–
7
answers
14
GATE CSE 2013 | Question: 37
In an IPv4 datagram, the $M$ bit is $0$, the value of $HLEN$ is $10$, the value of total length is $400$ and the fragment offset value is $300$. The position of the datagram, the sequence numbers of the first and the last bytes of the payload, ... , $2400$ and $2789$ First fragment, $2400$ and $2759$ Last fragment, $2400$ and $2759$ Middle fragment, $300$ and $689$
In an IPv4 datagram, the $M$ bit is $0$, the value of $HLEN$ is $10$, the value of total length is $400$ and the fragment offset value is $300$. The position of the datag...
31.9k
views
commented
Feb 4, 2016
Computer Networks
gatecse-2013
computer-networks
ip-addressing
normal
+
–
5
answers
15
GATE IT 2007 | Question: 27
The function f is defined as follows: int f (int n) { if (n <= 1) return 1; else if (n % 2 == 0) return f(n/2); else return f(3n - 1); } Assuming that arbitrarily large integers can be passed as a parameter to the function, consider the following ... values of $n \geq 1$. Which one of the following options is true of the above? i and iii i and iv ii and iii ii and iv
The function f is defined as follows:int f (int n) { if (n <= 1) return 1; else if (n % 2 == 0) return f(n/2); else return f(3n - 1); }Assuming that arbitrarily large int...
13.0k
views
commented
Jan 6, 2016
Programming in C
gateit-2007
programming
recursion
normal
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–
5
answers
16
GATE IT 2007 | Question: 7
Which of the following input sequences for a cross-coupled $R-S$ flip-flop realized with two $NAND$ gates may lead to an oscillation? $11, 00$ $01, 10$ $10, 01$ $00, 11$
Which of the following input sequences for a cross-coupled $R-S$ flip-flop realized with two $NAND$ gates may lead to an oscillation?$11, 00$$01, 10$$10, 01$$00, 11$
22.5k
views
commented
Jan 5, 2016
Digital Logic
gateit-2007
digital-logic
normal
flip-flop
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–
8
answers
17
GATE CSE 2007 | Question: 53
Consider the following two statements: P: Every regular grammar is LL(1) Q: Every regular set has a LR(1) grammar Which of the following is TRUE? Both P and Q are true P is true and Q is false P is false and Q is true Both P and Q are false
Consider the following two statements:P: Every regular grammar is LL(1)Q: Every regular set has a LR(1) grammarWhich of the following is TRUE?Both P and Q are trueP is tr...
35.7k
views
commented
Jan 3, 2016
Compiler Design
gatecse-2007
compiler-design
grammar
normal
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–
8
answers
18
GATE IT 2008 | Question: 28
Consider the following Hasse diagrams. Which all of the above represent a lattice? (i) and (iv) only (ii) and (iii) only (iii) only (i), (ii) and (iv) only
Consider the following Hasse diagrams. Which all of the above represent a lattice?(i) and (iv) only(ii) and (iii) only(iii) only(i), (ii) and (iv) only
15.1k
views
commented
Dec 27, 2015
Set Theory & Algebra
gateit-2008
set-theory&algebra
lattice
normal
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–
3
answers
19
GATE CSE 2008 | Question: 76
Delayed branching can help in the handling of control hazards For all delayed conditional branch instructions, irrespective of whether the condition evaluates to true or false, The instruction following the conditional branch instruction in memory is ... The first instruction in the taken path is executed The branch takes longer to execute than any other instruction
Delayed branching can help in the handling of control hazardsFor all delayed conditional branch instructions, irrespective of whether the condition evaluates to true or f...
18.0k
views
commented
Dec 18, 2015
CO and Architecture
gatecse-2008
co-and-architecture
pipelining
normal
+
–
2
answers
20
GATE CSE 2010 | Question: 34
The weight of a sequence $a_0,a_1, \dots, a_{n-1}$ of real numbers is defined as $a_0+a_1/2+ \dots + a_{n-1}/2^{n-1}$. A subsequence of a sequence is obtained by deleting some elements from the sequence, keeping the order of the remaining elements the same. Let $X$ denote the ... $X$ is equal to $max(Y, a_0+Y)$ $max(Y, a_0+Y/2)$ $max(Y, a_0 +2Y)$ $a_0+Y/2$
The weight of a sequence $a_0,a_1, \dots, a_{n-1}$ of real numbers is defined as $a_0+a_1/2+ \dots + a_{n-1}/2^{n-1}$. A subsequence of a sequence is obtained by deleting...
17.8k
views
commented
Dec 10, 2015
Algorithms
gatecse-2010
algorithms
dynamic-programming
normal
+
–
12
answers
21
GATE CSE 2015 Set 2 | Question: 48
A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is twice that of an AND/OR gate. The propagation delay of an AND/OR gate is ... adder is implemented by using four full adders. The total propagation time of this $4$-bit binary adder in microseconds is ______.
A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is twice that o...
62.1k
views
commented
Jul 20, 2015
Digital Logic
gatecse-2015-set2
digital-logic
adder
normal
numerical-answers
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–
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