Consider 5 stage pipeline which allow all instructions except branch instruction. Program contain 30% conditional instructions in which of the instructions doesn’t satisfy the condition. When the condition is false then the following instructions are overlapped. Processor stop fetching the following instruction after the branch instruction until target address is available. Target address is available at the end of the pipeline stage. All the stages are perfectly balanced with 20 GHz clock time. The average instruction execution time is ________________ nsec (upto 3 decimal place).