2 votes 2 votes How many clock cycle are needed in index addressing for getting memory content and effective address? CO and Architecture co-and-architecture control-unit + – Wanted asked Jan 6, 2017 edited May 2, 2020 by srestha Wanted 542 views answer comment Share Follow See all 7 Comments See all 7 7 Comments reply Show 4 previous comments Lokesh . commented Jan 6, 2017 reply Follow Share I m assuming 1 cycle per operation it might take more than that 0 votes 0 votes Wanted commented Jan 6, 2017 reply Follow Share cn u not have ny straight forward answer ...rather than if else? 0 votes 0 votes Lokesh . commented Jan 6, 2017 reply Follow Share it is generally mentioned in ques that add/sub take 2 cycles and mul/div takes 3 cycles so ALU can be of 2 or 3 cycles see this ques https://gateoverflow.in/25891/memory-addressing 0 votes 0 votes Please log in or register to add a comment.