retagged by
2,119 views
6 votes
6 votes

Carl Hamachar :

  • Time to access information in the cache = $1$ cycle
  • Main memory is constructed as $4$ interleaved modules
  • Cache block size of $8$ words.
  • In a cache miss, the first word of a block can be accessed from main memory in $7$ cycles and subsequent words take $4$ cycles per word
  • Time to send address to main memory = $1$ cycle
  • Cache hit ratio for data = 0.9
  • Cache hit ratio for instruction = 0.95
  1. $A$. What is the average memory access time for data?
  2. $B$. What is the average memory access time for instruction?
retagged by

1 Answer

Best answer
1 votes
1 votes
t=hC+(1-h)M

where C=time to access information from the cache

h=hit rate

M=Miss penalty or time required to bring the desired information into the cache after miss occurs.

Given h=0.95 for instructions and 0.9 for data, C=1 cycle

Let's find out M.

Miss penalty, M=time to send an address to main memory + time taken to access the required words + send the words to cache.

Given that it takes one clock cycle to send address to main memory. The memory is constructed as 4 interleaved modules.Since the block size is 8 words in the cache, in case of a miss we have to bring  8 words from memory. So after receiving the address, each module starts accessing the data. It takes 7 clock cycles to access first word. So after 7 clock cycles, each module has 1 word in its buffer which are transferred to the cache, one word at a time during the next 4 cycles. During these 4 cycles, the next word in each module is also accessed parallelly. Then it requires another 4 cycles to transfer these words to the cache.

Hence M=1+7+4+4=16 cycles.

So access time for instruction=0.95*1 + 0.05*16=1.75

for data=0.9*1+0.1*16=2.5
selected by
Answer:

Related questions