For all following questions we assume that:
- Pipeline contains 5 stages: IF, ID, EX, M and W;
- Each stage requires one clock cycle;
- All memory references hit in cache;
- Following program segment should be processed:
LD R1, 0(R2)
DADDI R1, R1, #1
SD 0(R2), R1
DADDI R2, R2, #4
DSUB R4, R3, R2
BNEZ R4, Loop
Calculate how many clock cycles will take execution of this segment on the simple pipeline without forwarding or bypassing ?