Pipelining Doubt

vaishali jhalani asked Jan 10, 2017 • retagged Nov 13, 2017 by Arjun

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I1: L R0, loc 1; R0 <= M[loc1]
I2: A R0, R0; R0 <= R0 +R0

WB of I1 and ID stage of I2....should be overlapping or not?

How to consider this case...as in gate previous questions answers are changing according to the given options?

CO and Architecture
pipelining
co-and-architecture

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vaishali jhalani asked Jan 10, 2017 • retagged Nov 13, 2017 by Arjun

vaishali jhalani

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Amit.kumar

commented Jun 5, 2017

i think answer wont change even either ID of i2 overlaps with EX stage or WB stage of i1.

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general doubt on pipelining
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sushmita asked Dec 17, 2018

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