TestBook Test Series

Question

Consider the following information about a hypothetical organization.

• Assume the cache is physically addressed
• TLB:hit rate is 95%,access time is 1 cycle
• Cache: hit rate is 90%,access time is 1 cycle
• When TLB and cache both get miss,page fault rate is 1%
• The TLB access and cache access are sequential.
• Main meory access time is 5 cycles
• Hard disk time is 100 cycles
• Page table is always kept in main memory.

Compute the average memory access time?

• 1 cycle
• 2 cycle
• 3 cycle
• 4 cycle

Comments

is it 1 cycle?

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@Sushan answer is 3

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will the answer differ if the cache is virtually addressed

Answer 1

Just refer the link here for actual working:

Avg TLB access time 

= 0.95 * (TLB access time + Avg  cache access time)

   +  0.05 * ( TLB access time +  Access page table + avg cache access time)   ............(1)

Avg cache time

= 0.9 * (cache access time ) 

  + 0.1 * ( cache access time + avg M.M access time)   ....................(2)

Avg M.M access time

= 0.99 * (M.M access time) 

  + 0.01 * (M.M access time + hard disk access time)

= 0.99 * (5) + 0.01* (5+100)

= 6 cycles  ......................(3)

From (2), 

Avg cache time

= 0.9*( 1 ) + 0.1*( 1 + 6 )

= 1.6 cycles  ................(4)

from (1),

Avg TLB access time 

= 0.95*( 1+ 1.6 ) + 0.05*( 1 + 5 + 1.6 )

= 2.85

$\approx$ 3 cycles

Answer 2

(0.95*1) + (0.5*0.9*(1+1)) + (0.5*0.1*0.99(1+1+5)) + (0.5*0.1*0.01*(1+1+5+100)) = 2.25   since cycle cannot be in decimalsl and less hence the answer is 3