MadeEasy Subject Test: CO & Architecture - Pipelining

Question

here  what about WB---> ID (operand forwarding) ?? i think this one have no meaning???

Comments

@Hradesh. 

There shouldnt be any stall in I2 because ID of I2 will get R2 from I0 at start of cycle. So, no issues.

So, above diagram is perfect.

They are asking max stalls in any of the instructions.

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So, without split phase, its 4 cycles

With split phase, its 2 cycles.

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@Hardesh , Yes ans should be 2 according to the question..as it is asking for maxmum stalls of any instruction...if  it was total stalls in execution of all 5 instructions then ans would have been more than or equal ( if no stalls in othe instruction) to 2 but here I have doubt in total stalls ..because they are saying only 2 but what about I0-I2 ( r2 ) and I2- I4 (r0) data dependency..  ..how these two are not causing any stalls...

@Sushant's logic also seems correct  to me...
@Kapil, @Arjun sir ..can you please see this ..

Answer 1

Following is how the execution will take place without split phase between PO-ID:

Note: Blue cells indicate stalls.

With split phase between PO-ID, following is the execution pattern:

Comments

@Vijay

PO buffer is modified at the end of 4th cycle.  But if we do forwarding from PO of I₀ to ID of I₃, ID of I₃ will get the correct data even before the 4th cycle has started or at the start of 4th cycle.

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^yes, looking fine ...  : )

Now lets wait for any experts for confirmation..

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@sushant, its fine !!