Virtual Gate Test Series: CO & Architecture - Cache Access

Question

my question is even in case of a miss the cache will still be accessed and then main memory, right? 
please explain this when to consider higher memory level access time and when not to consider it

Comments

if the question not containg hierarchy word then only use simultaneous otherwise use hierarchial.

It is hierarchial organization so if there is any miss we have to transfer to lower levels and then access it.

So answer is 42 only.

Answer 1

if nothing is mentioned, it is following simultaneous access in memory hirarchy .
Avg access time = cache hit * cache access time + missRate * hit rate in 2nd level * 2nd level access time

                          = .98 * 12 + .02 * 1 * 1500

                          =  41.76 ns