9.1k views

Consider the following program segment for a hypothetical CPU having three user registers $R_1, R_2$ and $R_3.$ $$\begin{array}{|l|l|c|} \hline \text {Instruction} & \text{Operation }& \text{Instruction size} \\&& \text{(in words)} \\\hline \text{MOV R_1,5000} & \text{R_1} \leftarrow \text{Memory[5000]}& \text{2} \\\hline\text{MOV R2(R1)} & \text{R2} \leftarrow \text{Memory[(R_1)]}& \text{1} \\\hline \text{ADD R_2,R_3} & \text{R2} \leftarrow \text{R_2 + R_3} & \text{1} \\\hline \text{MOV 6000,R_2} & \text{Memory[6000]} \leftarrow \text{R_2} & \text{2} \\\hline \text{HALT} & \text{Machine Halts} & \text{1} \\\hline \end{array}$$Consider that the memory is byte addressable with size $32$ bits, and the program has been loaded starting from memory location $1000$ (decimal). If an interrupt occurs while the CPU has been halted after executing the HALT instruction, the return address (in decimal) saved in the stack will be

1. $1007$
2. $1020$
3. $1024$
4. $1028$

edited | 9.1k views

Option is D.

Word size is $32$ $bits$ ($4$ $bytes$). Interrupt occurs after execution of HALT instruction NOT during,  So address of next instruction will be saved on to the stack which is $1028$.

(We have $5$ instructions starting from address $1000$, each of size $2, 1, 1, 2, 1$ totaling $7$ words $= 7 *4 =28$ $bytes$).

$1000+ 28 = 1028$,

$1028$ is the starting address of NEXT Instruction .

After HALT instruction CPU enters a HALT state and if an interrupt happens the return address will be that of the instruction after the HALT.

References :

by Boss (13.5k points)
selected by
0
after fetching halt instruction, PC value will become 1028. but while executing halt instruction pc value again goes to 1024 because HALT is unconditional jump to itself, so if interrupt comes while executing halt instruction, pc value will be 1024.

+2

.If an interrupt occurs while the CPU has been halted AFTER executing the HALT instruction, then the return address (in decimal) saved in the stack will be starting address of next instruction that is 1028 .

+6

But there is no next instruction after HALT @Bikram sir as mentioned...Hence by default the meaning of HALT as we know is looping within itself so next address will be same as that of HALT as there is no instruction after HALT in the given question..

Hence 1028 address means there is some next sequential instruction after HALT which is a wrong claim with respect to the given question..

Hence 1024 should be correct..

+16
Notice --> "Interrupt comes during the halt instruction" and "Interrupt comes after halt instruction", both are same. Because interrupt are served only after execution of current instruction.
0

Habibkhan Bhai,

Answer may very depending according to architecture. But i think in most of the cases PC value will not remain 1024 if interrupt comes otherwise it will go in infinite loop.

0
What should be the final answer 1024/1028
+2

Consider that the memory is byte addressable with size 32 bits

with *word of size 32 bits.

0
@Bikram sir when memory is word addressable of size 32 bits. Then why are you treating it as byte addressable?
+1

Lots of speculation as to which is correct : 1024 or 1028.

Read this on x86 instruction set reference

http://c9x.me/x86/html/file_module_x86_id_134.html

0
0
now it is clear how 1028 will be the answer thanks bikram sir
0
0
what is the ans in answer key of gate paper.
+1

I am still confused! after reading all these references:

The references says:

If an interrupt (including NMI) is used to resume execution after a HLT instruction, the saved instruction pointer (CS:EIP) points to the instruction following the HLT instruction.

But in the question it is no where mentioned that this interrupt is used to get the system out of the halted state! it just says that interrupt occurs after the execution of halt instruction. what if it is some other interrupt?

and what if the reset instruction is used to get the system out of the halted state?

0

@Bikram sir,

Although I understood the solution. The link you provided as a reference is not working.

0
In above question if halt occurred during the execution of the halt instruction than what could be the return address pushed onto the stack
0
During execution of HALT instruction value of PC again 1024(starting address  of HALT)..So during execution of HALT instruction interrupt occurs,So PC value 1024 must pushed into the stack,not 1028. This is exception for HALT instruction
0
I think in both cases the answer should be same as the interrrupt is processed only after the execution of current instruction
0

https://x86.puri.sm/html/file_module_x86_id_134.html

In this link, Instruction resumes is the sense of executing interrupt service routine, which is not in the actual instruction sequence or program.after servicing interrupt service routine, it will come back again at halt instruction.

we're wrongly interpreting the Instruction resumes term.

ans should be 1024.