8.2k views

Consider the following program segment for a hypothetical CPU having three user registers $R_1, R_2$ and $R_3.$

\begin{array}{|l|l|c|} \hline \text {Instruction}  &  \text{Operation }& \text{Instruction size} \\&& \text{(in words)} \\\hline \text{MOV $R_1,5000$} & \text{$R_1$} \leftarrow  \text{Memory$[5000]$}& \text{$2$} \\\hline\text{MOV $R2(R1)$} & \text{$R2$} \leftarrow  \text{Memory$[(R_1)]$}& \text{$1$} \\\hline \text{ADD $R_2,R_3$} & \text{$R2$} \leftarrow  \text{$R_2 + R_3$} & \text{$1$} \\\hline \text{MOV $6000,R_2$} & \text{Memory$[6000]$} \leftarrow  \text{$R_2$} & \text{$2$} \\\hline \text{HALT} & \text{Machine Halts} & \text{$1$} \\\hline \end{array}

Consider that the memory is byte addressable with size $32$ bits, and the program has been loaded starting from memory location $1000$ (decimal). If an interrupt occurs while the CPU has been halted after executing the HALT instruction, the return address (in decimal) saved in the stack will be

1. $1007$
2. $1020$
3. $1024$
4. $1028$
edited | 8.2k views
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Notice --> "Interrupt comes during the halt instruction" and "Interrupt comes after halt instruction", both are same. Because interrupt are served only after execution of current instruction.
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Consider that the memory is byte addressable with size 32 bits

with *word of size 32 bits.

Option is D.

Word size is $32$ $bits$ ($4$ $bytes$). Interrupt occurs after execution of HALT instruction NOT during,  So address of next instruction will be saved on to the stack which is $1028$.

(We have $5$ instructions starting from address $1000$, each of size $2, 1, 1, 2, 1$ totaling $7$ words $= 7 *4 =28$ $bytes$).

$1000+ 28 = 1028$,

$1028$ is the starting address of NEXT Instruction .

After HALT instruction CPU enters a HALT state and if an interrupt happens the return address will be that of the instruction after the HALT.

References :

edited
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But there is no next instruction after HALT @Bikram sir as mentioned...Hence by default the meaning of HALT as we know is looping within itself so next address will be same as that of HALT as there is no instruction after HALT in the given question..

Hence 1028 address means there is some next sequential instruction after HALT which is a wrong claim with respect to the given question..

Hence 1024 should be correct..

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Habibkhan Bhai,

Answer may very depending according to architecture. But i think in most of the cases PC value will not remain 1024 if interrupt comes otherwise it will go in infinite loop.

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What should be the final answer 1024/1028
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@Bikram sir when memory is word addressable of size 32 bits. Then why are you treating it as byte addressable?
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Lots of speculation as to which is correct : 1024 or 1028.

Read this on x86 instruction set reference

http://c9x.me/x86/html/file_module_x86_id_134.html

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now it is clear how 1028 will be the answer thanks bikram sir
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what is the ans in answer key of gate paper.
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I am still confused! after reading all these references:

The references says:

If an interrupt (including NMI) is used to resume execution after a HLT instruction, the saved instruction pointer (CS:EIP) points to the instruction following the HLT instruction.

But in the question it is no where mentioned that this interrupt is used to get the system out of the halted state! it just says that interrupt occurs after the execution of halt instruction. what if it is some other interrupt?

and what if the reset instruction is used to get the system out of the halted state?

Word size is =32 bits (4 bytes)

Given that, memory is byte addressable, Therefore memory layout of this program is-

This layout says-

 Instruction Starting address Ending address I1: 1000 1007 I2: 1008 1011 I3: 1012 1015 I4: 1016 1023 I5: 1024 1026

This is about how this program is stored in memory.

Now, Lets see what HALT do.

Halt internally invokes JMP like this-

 𝓁𝟣: Jmp 𝓁𝟣

(YES, it is infinite loop)

Halt instruction (unconditionally) jumps to same address of the instruction itself. And as an user point of view, program is terminated, but as a CPU point of view, it goes in infinite loop.

at the time Halt instruction (I5)  is being fetched, value of PC = next sequential address which is 1028.

But once halt is executed PC is again loaded to address of 𝓁𝟣, which is 1024.

(Note that: CPU does not service interrupt in between of any instruction, even if interrupt comes at time of executing I5, but CPU will service it only after instruction execution is completed.)

Now value of PC = 1024, and this value will be pushed to Stack, before servicing Interrupt.

(Remember one thing- If an Interrupt occurs at Jump instruction then the address saved onto the stack is the target address. Otherwise sequential address. )

reshown by
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Correct expaination what I needed.Thanks :)
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AWESOME EXPLANATION. THANX A LOT
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awsome ans

elaborte thiz with ex :(Remember one thing- If an Interrupt occurs at Jump instruction then the address saved onto the stack is the target address. Otherwise sequential address. )
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Thnks :)
which example u need here ?
This is true for all instruction. You can take any set of instruction with atleast one of the Jump instruction, And see how PC is getting updated.
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@ arjun sir- "If an interrupt (including NMI) is used to resume execution after a HLT instruction, the saved instruction pointer (CS:EIP) points to the instruction following the HLT instruction." this is according to the reference given by you. So answer should be 1028?? right sir??
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yes @sushmita

answer is 1028 only , option D

From the x86 instruction manual ---- > If an interrupt  is used to resume execution after a HLT instruction, the saved instruction pointer  points to the instruction following the HLT instruction. [1]

here in this question they also asked  ..If an interrupt occurs while the CPU has been halted AFTER executing the HALT instruction,

then the return address (in decimal) saved in the stack will be starting address of next instruction that is 1028 .

References:

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thanx sir.
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what will  be the answer if the interrupt comes during the execution of halt instruction.

1024 or 1028?
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Because if an interrupt occurs, the CPU has been halted after executing the HALT instruction the return address 1024 saved in the stack

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