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Consider a small two-way set-associative cache memory, consisting of four blocks. For choosing the block to be replaced, use the least recently used (LRU) scheme. The number of cache misses for the following sequence of block addresses is:

$8, 12, 0, 12, 8$.

  1. $2$
  2. $3$
  3. $4$
  4. $5$
in CO and Architecture by Veteran (52.1k points)
edited by | 3.8k views
0
what will be the number of conflict cache miss ? is it 2?
0
@akshat sharma...No, total cache miss is 4 but conflict cache miss is only one for the last element 8.

2 Answers

+16 votes
Best answer
We have $4$ blocks and $2$ blocks in a set

$\implies$ there are $2$ sets. So blocks will go to sets as follows:
$$\begin{array}{|c|c|} \hline \textbf {Set Number} &  \textbf{Block Number} \\\hline \text{0} & \text{0,8,12}  \\\hline\text{1} &  \\\hline \end{array}$$
Since the lowest bit of block address is used for indexing into the set, so $8, 12$ and $0$ first miss in cache with $0$ replacing $8$ (there are two slots in each set due to $2-\text{way}$ set) and then $12$ hits in cache and $8$ again misses. So, totally $4$ misses.

Correct Answer: $C$
by Veteran (416k points)
edited by
+1
How can tag bits be the lowest most bits ? Tag bits are the upper most bits. Lower most bits is the index. Here as there are only 2 sets, index bit = 1. isn't it ?
+1
Yes. You are right. I have corrected it. It's index or set bits and not tag bits. Tag bits are the upper bits and relevant to identify which block is currently present in a cache block. In this question this part is not asked and we just need to identify the 1 index bit.
+1
Very Nice explanation...
0
Sir, did you use LRU into it?
+4 votes
2 way set associative

4 blocks

Set size = # of blocks / # of sets

            = 4/2 = 2

So Block addresses will be divided by 2 ... On the basis of their remainder we will place those blocks in the sets .. applying LRU approach ... answer will be 4 ..
by Boss (11.5k points)
+1

This one ....

Answer:

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