In this question, it is explicitly mention that " The processor takes 900 clock cycles to complete DMA transfer " .
CPU is usually the master and in this DMA case, instead of this master, another master DMA takes its place. So you can see that CPU is also a processor, DMA controller is also a processor but then DMA controller is a special purpose processor meant only for data transfer, nothing else.
CPU is kept in suspended animation and it is going to wait until the DMA controller releases , until the block of data transfer is over, the CPU will be kept in suspended animation and at the end of the block transfer the controller will release the bus to the CPU.
So it means CPU is idle theoritacally in this time period when DMA transfer the data but practically CPU is not idle , it is doing some other task through other bus .. but for our convenience we just think that CPU is siting idle in this time period .