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A 4-stage pipeline has the stage delays as $150$, $120$, $160$ and $140$ $nanoseconds$, respectively. Registers that are used between the stages have a delay of $5$ $nanoseconds$ each. Assuming constant clocking rate, the total time taken to process $1000$ data items on this pipeline will be:

1. $120.4$ $microseconds$

2. $160.5$ $microseconds$

3. $165.5$ $microseconds$

4. $590.0$ $microseconds$

edited | 2.8k views
+1

i know a formula ,

total time in a pipeline = ((no of segments * max time delay in a pipeline)+ (number of intermediate buffers * max buffer delay)[for 1 instruction]  + (total instructions -1) x (max time delay of a pipeline stage)

on substitution we get,

total time = ((4 * 160) + (3*5)) + (999 * 160) = 160495 ns = 160.495  ==> 160.5 micro secs .

isnt this correct ??

anybody plz ..

thanks

+7
more simple formula

(no of stage-1+no of jobs)*cycle time of pipe

cycle time of pipe=max{stage delay+buffer delay}=160+5

you will get={3+1000}*165=165495 ns=165.495 micro sec
0
i get it, but that formula i read it from a faculty , but forget the formula , the answer should hav been the same right ? why we get two different answers ?
+1
I really have no idea, what i knew i shared,maybe you can use simpler version,it works for me always,so it will work for you too.
0
Why are we considering the cycle time as 165ns. It is clearly given that the registers have been used in between the stages and hence, no register at the last stage.

so the max delay should be 160ns?

Pipelining requires all stages to be synchronized meaning, we have to make the delay of all stages equal to the maximum pipeline stage delay which here is $160$.

Time for execution of the first instruction $= (160+5) * 3 + 160 = 655$ ns ($5$ ns for intermediate registers which is not needed for the final stage).

Now, in every $165$ ns, an instruction can be completed. So,

Total time for $1000$ instructions $= 655 + 999*165 = 165.49$ microseconds
edited by
0
sir,

" Time for execution of the first instruction = (160+5) * 3 + 160 = 655 ns (5 ns for intermediate registers which is not needed for the final stage). "

the first instruction cycle is 165*4=660
+1
@Arjun SIr..

One doubt.Here it is not mentioned that pipeline is synchronous.then why we are considering all stage taking 165ns  time?
+3

Question mentions it

Assuming constant clocking rate,

Even otherwise, unless specified otherwise we should assume this.

0
Okk..thank you
+6

^@Shubham,

Registers that are used at the end of every stage have a delay of 5ns each then for the first instruction cycle needed should be  = 165*4=660..

but here it is given that Registers that are used between the stages have a delay of 5 nanoseconds each

Am I right @Arjun sir .. ?

0
$n=1000$, $k=4$, $t_p=160+5=165$. Putting in the formula:

$(k+(n-1))t_p \rightarrow (4+(999))165=165,495ns.$
But we have to remove 5ns of the 4th stage of first instruction. Final answer is 165.490 microsec
0
I don't think we need to subtract the 5ns for the first instruction because the calculation of the clock time period includes both maximum delay of a stage and delay of the register.

And even if we do not consider including the register delay in the calculation of the time period, it is for the last instruction whose register delay (of the last stage) would not be counted, not for the first instruction.
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Every instruction following the first instruction is coming out after every 165ns, which includes the last instruction too.

We need to subtract the 5ns because there are 3 buffers between the 4 stages. There is no buffer after the 4th stage, and hence first instruction won't be needing the 5ns.
0
@Arjun sir... What is the reason behind the taking of max delay among the delays my point of view is ....We do not consider the next stage without completing the previous as that is a rule we must consider all the stage delays independently sir plzz explain it sirr
+1 vote
Delay between each stage is 5 ns.
Total delay in pipline = 150 + 120 + 160 + 140 = 570
Total delay for one data item = 570 + 5*3 (Note that there are 3 intermediate registers)
= 585
For 1000 data items, first data will take 585 ns to complete and rest
999 data will take max of all the stages that is 160 ns + 5 ns register delay

Total Delay = 585 + 999*165 ns which is approximately 165.5 microsecond.
0
Wrong
+1 vote
Lets first instruction will take all four stages(4cycle) and rest 999 instruction will be completed in every clock cycle.

TT(total time)=First instruction x Number of cycle x Duration of each cycle + 999 x Number of cycle x Duration of cycle

TT=1 x4x(160+5)+999x1x165 ns

TT=165,495 ns

TT=165.495 micro second

//Max time period=Max_duration(150,120,160,140)+register delay=165ns
ans c)