Testbook

Question

I am getting numerator as 6.5 in this way:

= 0.9 * (#stages for non-branch instruction) + 0.1 * (#stages for branch instructions)

= 0.9 * 6   + 0.1 * (6 + 5)

= 6.5

Comments

The question also sounds ambigous. They say that branch instructions cant overlap with non-branch instructions.

Now, they say penalty is 5 cycles.

Now, 5 cycles penalty when overlapping of branch instructions is done(i.e total 11 stages) or without it( i.e total 6+6+5=17 stages) ?

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Numerator should be time without pipelining.

So, it should be

0.9 * (#stages for non-branch instruction) + 0.1 * (#stages for branch instructions) = 0.9 * 6   + 0.1 * 6

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Got it ...making blunders :(

Answer 1

Simple approach :

Speedup  =  CPI_{non pipeline} * Cycle time_{non pipeline} /  [ CPI_pipeline * Cycle time_pipeline ]

Now by default Cycle time_{non pipeline}  =  Cycle time_pipeline

Also no of cycles required / instruction in non pipelined system  =  No of stages( Pipeline )

                                                                                             =  6 here

And by default , CPI_{ideal pipeline}  =  1

And now we find stall / instruction                                            =  Branch frequency * Branch penalty..

                                                                                             =  0.1 * 5

                                                                                             =  0.5

Hence CPI_pipeline    =   1 + 0.5   =  1.5

So 

Speedup  =  CPI_{non pipeline} * Cycle time_{non pipeline} /  [ CPI_pipeline * Cycle time_pipeline ]

               =  6 / 1.5

               =  4

Hence 4 is the correct answer..

Comments

@Habib. Thanks. I miscalculated for non-pipelined processor :)

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Could you address the ambiguity immediately below the question?