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64 word cache and main memory is divided into 16 words block.The access time of cache is 10ns/word and for main memory is 50ns/word. The hit ratio for read operation is .8 and write operation is.9. Whenever there is a miss in cache, associated block must be brought from main memory to cache for read and write operation. 40% reference is for write operation. Avg access time if write through is used.

asked in CO & Architecture by Active (1.1k points)
edited by | 1.2k views
what is the default memory organization- simultaneous or hierarchical?? this is the biggest doubt.. PLzzz Plzzz some one clear it.

Sir i have small confution

TavgR=hr×tc+(1−hr)×(tm+tc)  in given formula what tc is. tc=cache access time before new block come to main memory or cache acces time after new block is come to MM and then access is taken from cache.

I think in given formula will be hr*tc + (1-hr)*(tm+2*tc) bcoz in case of miss cache is access 2 time, before block came from MM and after block come into MM.

please clear my confution @Arjun

by default we use simultaneous .
By default we use hierarchical, it is more practical.

simultaneous is like parallel access which is not easily practical inside a CPU where things happen at nanosecond intervals.

1 Answer

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Best answer
Cache access time = 10 ns
1 block main memory access time $= 50\times 16 = 800 ns$ (as from main memory, entire cache block is retrieved)

Then use this formula
$T_{avg_R} = h_r \times t_c+(1-h_r)\times (t_m + t_c) = 0.8 \times 10 + 0.2 \times (800 + 10) = 170 ns$ (Hierarchical access is default in case of read)

Whenever cache is missed, data (entire cache block) must come from main memory for write as per question. Also for all write operations, one word of data is written to main memory as cache is WRITE THROUGH. In WRITE THROUGH cache since main memory is always updated, memory arrangement is simultaneous and hence cache access time need not be considered (as it should be smaller than main memory access time and both happens in parralel).

$T{avg_W} = h_w\times t_m + (1-h_w)  (t_m + 800 )$

$= 0.9 \times 50 + 0.1 \times 850 = 130 ns$

$T_{avg}= f_r\times T_{avg_R}+ f_w\times T_{avg_W} = 0.6 \times 170 + 0.4 \times 130 = 154 ns.$
answered by (199 points)
edited by
whole cache is not fetched- only cache line is fetched.
it is 64 word cache..okay,but we will fetch only 1 word..so..

but suppose it was given that maim memory access=20ns,but when a miss occurs,we need to bring entire block, then it would have neeb multiplied(for MM)
Someone please tell me what is the actual meaning of cache access time . Is it the time required to fetch a byte or time required to search cache or is it the sum of both?

Xylene

cache access time  includes :

 The time required to search cache  and then fetch a byte ,

yes it is sum of both .

64 word cache and main memory  and 16 word block

 

then shouldnot cache contains 4 blocks only? and this also same for main memory?

@arjun sir, please confirm.

As it is mentioned in the question, "Whenever there is a miss in cache, associated block must be brought from main memory to cache for read and write operation".

In case of read miss, we will spend 10ns in cache to check it is present or not + 800 ns to bring the block to cache + further 10 ns to read the required data.

In case of write hit, 50 ns to write the word in the main memory. ( Assuming simultaneous because it is write through policy).

In case of write miss, 50 ns to write the word in the main memory + 800 ns to get the block into the cache.

@Hemant

In case of read miss, we will spend 10ns in cache to check it is present or not + 800 ns to bring the block to cache + further 10 ns to read the required data.
 

We don't need to add 10ns two times. When data is sent from main memory to cache it can simultaneously go to CPU also (sniffing technique). Otherwise even if a repeat read happens from cache; we don't need to assume hierarchical access anymore and we can assume simultaneous access (refer examples in Hamacher). i.e., in all cases add the cache times only once for a miss.

In case of write miss, 50 ns to write the word in the main memory + 800 ns to get the block into the cache.

yes, for this question. But it will be really rare for such an assumption to be given in an actual GATE question nowadays. So, read the question really carefully during GATE -- most of the 5+ year old questions are kind of not relevant in this area now. Keep the concepts clean; you can answer in GATE even if not in test series.

 

 

Sir, in write-through policy, Processor takes a lot of time because of Memory Write.

Is this problem can be solved by using the write buffer to hold those write requests and to be done by some other units.? And allow the processor to proceed to next instruction immediately.
yes, practically the processor does not really wait. You can think like this "if you can think of an optimization; the professors and researchers working just on this problem would have thought of it already and implemented them."
Thank you sir :)


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