1 votes 1 votes Digital Logic digital-logic clock-frequency flip-flop virtual-gate-test-series + – Sheshang asked Jan 18, 2017 edited Apr 14, 2019 by Lakshman Bhaiya Sheshang 519 views answer comment Share Follow See all 4 Comments See all 4 4 Comments reply Rahul Jain25 commented Jan 18, 2017 reply Follow Share Was the given answrr 31.7 Mhz?? 0 votes 0 votes Sheshang commented Jan 18, 2017 reply Follow Share 54.05 0 votes 0 votes Sheshang commented Jan 18, 2017 reply Follow Share what these TpLH and TpHL means? related to high-low something?? 0 votes 0 votes arch commented Aug 14, 2017 reply Follow Share hw u get ans can u plz elaborate? 0 votes 0 votes Please log in or register to add a comment.
0 votes 0 votes max flip-flop delay+max combinational path delay+max set up time<=clock period 2+15(1)+1.5<=clock period clock period=18.5 t=1/f=1/18.5=54.05 MHZ Mritunjay Ashish answered Sep 25, 2019 Mritunjay Ashish comment Share Follow See all 0 reply Please log in or register to add a comment.