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in Digital Logic by Active (3.5k points)
edited by | 156 views
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Was the given answrr 31.7 Mhz??
0
54.05
0
what these TpLH and TpHL means? related to high-low something??
0
hw u get ans can u plz elaborate?

1 Answer

0 votes
max flip-flop delay+max combinational path delay+max set up time<=clock period

2+15(1)+1.5<=clock period

clock period=18.5

t=1/f=1/18.5=54.05 MHZ
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