yes roughly we can say MUX and OR gate works parallely in cache memory . OR gate used to TAG comparison to select set, while MUX is used for select which data bits are valid.
In hit data is present in cache . So, why do u think it is disadvantage of set associative cache?
If data already present in cache, then just read the data once, and valid bit will be 0. But u have to go perticular set and get the data. Moreover if data is not present in data buffer , u have to check different policy - either write back or write through policy, to see which is better to get data in less time.
Another one thing is, write allocate and write not allocate
If data is already stored, but not loaded yet - and we are getting hit- then we can say it is write not allocate.
Otherwise if we need to load data everytime to get a hit, that is write allocate.
In all these cases we have to include MUX and OR gate delay too, because those are tools select lines , as per given policy. So, if both delays are given then must have to include them.
yes in full associtive cache no indexing is required. Data can place anywhere in cache. No perticular arrangement is there. But TAG and word bit are there. Means MUX and OR bit used here too. Moreover they are interrelated. Selected bit of MUX is used in OR gate to get which data is hit and which one miss.