- What is the size of $MUX$ needed in direct mapped cache ?
For ex :- | Tag = $17$ | line = $10$ | word = $5$ |
Diagram Reference :- Direct mapped cache with multi word block
- In set associative cache, Do MUX and OR gate work in parallel,i.e
What i mean to ask that data is loaded in MUX and OR checks for hit/Miss parallely ? If hit, then data is given . Then, shouldn't this be a disadvantage for set associative cache ?
- Also, if MUX and OR gate work parallely, then Hit latency includes both delays ?
Diagram Reference :-
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- Also, any reason/explaination regarding below image ?